N. Wehn, J. Biesenack, T. Langmaier, M. Muench, M. Pilsl, S. rumler, and P. Duzy. Scheduling of behavioural VHDL by retiming techniques. In Proceedings EuroDAC 94, pages 546 -- 551, September 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....India, Jan. 8 11, 1996. 19] P. Ellervee, A. Hemani, A. Kumar, B. Svantesson, J. berg, H. Tenhunen, Controller Synthesis in Control and Memory Centric High Level Synthesis System , In Proc. of the 5th Biennial Baltic Electronic Conference, pp 393 396, Tallinn, Estonia, Oct. 7 11, 1996. [20] F. Bueno, J. berg, A. Kumar, M. Torkelsson, High Level Synthesis of a 1 Mbps Direct Sequence SpreadSpectrum RAKE Receiver , In Proc. of the 6th Workshop on Synthesis And System Integration (SASIMI 96) pp 170 177, Fukuoka, Japan, Nov. 25 26, 1996. 21] J. berg, A. Kumar, A. Jantsch, An ....

....units. In telecommunication systems, targeted for routing, switching etc. the functionality is dominated by control decision and interactions with memory, with little or no arithmetic operations. There has been several suggestions on how to extend HLS to cope with control dominated functionality [17, 18, 19, 20, 21, 22]. While the work by W. Wolf [17] presents a model for performing behavioural synthesis, the other papers address the problem of global scheduling of the of the datapath operations into control states. Figure 1.4. The principles of High Level Synthesis X(15 downto 1) X(14 downto 0) Xin; ....

N. Wehn, J. Biesenack, T. Langmaier, M. Mnch, M. Pilsl, S. Rumler, P. Duzy, "Scheduling of Behavioural VHDL by Retiming Techniques", In Proc. of EuroDAC'94, pp. 546-551, Sept. 1994.

....large. The tree based scheduler considers data dependencies and thus it is not constrained by the initial order of the operations. It also considers resource constraints but no constraints involving operator delays and i o event ordering are considered. 73 A different approach is presented in [WBL94] which examines control flow as well as data flow and formulates the scheduling constraints as linear (in)equalities. This results in an ILP problem with a special form, which lends itself to a polynomial time solution. However, control flow paths (and data flow chains in this case) need to be ....

....Data dependency information is not needed in order to prevent the operations to be artificially constrained by the order inherent in the control flow. In [BRN97] the data dependency information is used locally, at the basic block level, to optimally reorder the operations. Whereas in [YeWo96] and [WBL94] the data dependency information is used at a global level and the operations can be reordered and can even move across the basic blocks. In [WBL94] since loops are opened before scheduling, the data dependencies are also acyclic and are handled without difficulty. In [YeWo96] on the other ....

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N. Wehn, J. Biesenack, T. Langmaier, M. Mnch, M. Pilsl, S. Rumler, P. Duzy, "Scheduling of Behavioural VHDL by Retiming Techniques", Proc. of EURO-DAC'94, pp. 546-551, ACM/IEEE, September 1994.

....by Leiserson and Saxe in [8] in order to solve Problem 1 for systolic circuits (unit delay circuits with at least one register between two functional units) Their solution, using the Bellman Ford algorithm, requires O(jEjjV j) time. Wehn et al. linked high level synthesis and retiming in [2], using the correspondence between wait until statements and registers. Using the conditions 7 de ned by Leiserson and Saxe, they stated di erent problems, like As Soon AsPossible scheduling or minimization of registers, as linear programming problems. They expressed these problems with various ....

J. Biesenack, T. Langmaier, M. Munch, and N. Wehn. Scheduling of behavioural VHDL by retiming techniques. In Proceedings of the EuroDAC '94, pages 546-551, September 1994.

....for CMIST has to deal with data flow as well as control flow. The need to consider control flow as well as data flow makes the CMIST scheduling essentially global and hence more complex. Recent years have seen development of some new techniques for scheduling of control dominated circuits [2, 3, 4]. All these aim at globally scheduling the operations (control as well as data) into control states followed by generation of an FSM based controller. Path based scheduling was introduced by [2] as a mechanism to do global scheduling. In this method, all control flow paths are identified and ....

....ordering are considered. Figure 1. CMIST synthesis strategy Output FSM in VHDL Verilog Extract Arithmetic Components Schedule Perform State Marking Allocate and Extract DP Components and Memory Extract Control Flow (XFC) optional optional 3 An altogether different approach is presented in [4] which formulates the scheduling problem as an ILP problem. A wide range of constraints and data dependencies are shown to map to linear constraints of ILP. The ILP formulation here has a special form which lends itself to a polynomial time solution. This is a clear advantage over path based and ....

N.Wehn, J.Biesenack, T.Langmaier, M.Münch, M.Pilsl, S.Rumler, P.Duzy. Scheduling of Behavioural VHDL by Retiming Techniques. Proceedings of EURO-DAC'94, pp.546-551, ACM/IEEE, September 1994.

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N. Wehn, J. Biesenack, T. Langmaier, M. Muench, M. Pilsl, S. rumler, and P. Duzy. Scheduling of behavioural VHDL by retiming techniques. In Proceedings EuroDAC 94, pages 546 -- 551, September 1994.

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N. Wehn, J. Biesenack, T. Langmaier, M. Muench, M. Pilsl, S. Rumler, and P. Duzy. Scheduling of behavioural VHDL by retiming techniques. In Proceedings EuroDAC 94, pages 546 -- 551, September 1994.

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