J. Pino, Michael C. Williamson, and Edward A. Lee. Interface Synthesis in Heterogeneous System-Level DSP Design Tool. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....approach, a software or a hardware simulator interacts with PeaCE, the cosimulation backplane, not knowing the existence of the counterpart. The backplane monitors and manages all communication events between the software and the hardware simulators. On the other hand, Ptolemy group of U.C. Berkeley[8] devised a common interface mechanism between any pair of simulators so that they also achieve the same reduction of interface modules to N. Their approach is called heterogeneous simulation[12] Therefore, as shown in figure 2, while the cosimulation is in progress, several UNIX processes are ....

....intervention. It distinguishes our approach from Sari s approach of Carnegie Mellon University[11] ffl No restriction on VHDL specification : A previous work from U.C. Berkeley restricted the VHDL program, which is generated from a program graph with SDF semantics, to a single thread of control [8]. Even though this approach schedules the communication statically for deadlock avoidance as well as runtime performance improvement, it is too restrictive for general applications. In [8] only one sequential process is running on the VHDL simulator. Our VHDL specification has no such ....

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J. Pino, Michael C. Williamson, and Edward A. Lee. Interface Synthesis in Heterogeneous System-Level DSP Design Tool. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1996.

....and cost effectiveness of a partition is examined. On each iteration of codesign process, a new partition is made, which requires the rebuilding of the interface between two subgraphs. Since making an interface is tedious and error prone work, it is desirable to generate the interface automatically[5]. PeaCE provides designers with automatic interface generation facility [10] After partitioning, each subgraph is modified in order to add interface nodes at the sub system boundary. From the partitioned graphs, C and VHDL codes are generated. The interface node to be added is chosen from the ....

....and the generated VHDL code from the hardware graph is passed to the VHDL simulator for hardware simulation. To combine two concurrent simulators (C process and VHDL simulator) PeaCE introduces and implements a backplane concept, which reduces the number of interface module from N(N 1) to N[5, 10]. 2.4 Evaluation, Synthesis and Prototyping With simulation results, the evaluation module makes a decision whether the current partition satisfies the system requirements. Unless they are satisfied, the codesign process continues to iterate from the partition stage to the evaluation stage. ....

J. Pino, Michael C. Williamson, and Edward A. Lee. Interface synthesis in heterogeneous system-level dsp design tool. IEEE International Conference on Acoustics, Speech,and Signal Processing, 1996.

....is no standard interface defined so that new communication code needs to be defined to integrate a new simulator. Also, data exchange between the software and the hardware parts is hidden in the simulated program. So, it is not visible to be probed. For arbitrary connection of various simulators, [8] defines a standard interface through which each simulator can communicate with others. In their approach, they Implementation Rules Synchronization Rules Communication Rules Cosimulation Environment Program Simulators Link Modules SIM A SIM B Backplane Fig. 2. The architecture of cosimulation ....

....VCI tool are developed in order to generate VHDL entities from the interface description called VCI specification. However, even in this approach, designer should make the I O descriptions whenever the graph topology is modified. The most automated approach of interface generation is studied in [8]. In their work, however, the application specification semantics are limited to a specific class of dataflow known as SDF[12] Within the limitation of SDF semantics, they are able to statically schedule the graph and guarantee a deadlock free execution. We aim to develop a technique of automatic ....

J. Pino, Michael C. Williamson and Edward A. Lee, "Interface Synthesis in Heterogeneous System-Level DSP Design Tools", IEEE International Conference on Acoustics, Speech, and Signal Processing, 1996

....is no standard interface defined so that new communication code needs to be defined to integrate a new simulator. Also, data exchange between the software and the hardware parts is hidden in the simulated program. So, it is not visible to be probed. For arbitrary connection of various simulators, [10] defines a standard interface through which each simulator can communicate with others. In their approach, they use a C process as a standard interface so that a simulator should send the data to an automatically synthesized C process from which the destination simulator receives it. Their ....

....found in [12] where the VCI tool is developed in order to generate VHDL entities from the interface description called VCI specification. However, a designer should make the I O descriptions whenever the graph topology is modified. A more automated approach of interface generation is studied in [10]. In their work, however, the application specification semantics are limited to a specific class of dataflow known as SDF[7] Within the limitation of SDF semantics, they are able to statically schedule the graph and guarantee a deadlock free execution. We aim to develop a technique of automatic ....

J. Pino, Michael C. Williamson and Edward A. Lee, "Interface Synthesis in Heterogeneous System-Level DSP Design Tools", IEEE International Conference on Acoustics, Speech, and Signal Processing, 1996.

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