J. Cong and Y. Ding, "On nominal delay minimization in LUT-based FPGA technology mapping," Integration---The VLSI J., vol. 18, pp. 73--94, 1994. Home/Search Document Details and Download
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Parallel Performance Directed Technology Mapping for FPGA - Lemarchand (Correct)
....of cascaded lut in the boolean network. More accurate models include the net delay model [4] in which each node (net) has a pre assigned (thus also static) delay, the general delay model [13] that associates a propagation delay to each connection between terminals, and the nominal delay model [3] where the cost of a net is proportional to its number of terminals. This last model is dynamic since the delay of a net varies with the covering solution of the associated node. All except the unit delay model take into account both the delays induced by the lut and those of the interconnections ....
J. Cong and Y. Ding. On nominal delay minimization in lut-based fpga technology mapping. Integration -- The VLSI Journal, 18:73--94, November 1994.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED.. - With Efficient Initial Self-citation (Cong) (Correct)
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J. Cong and Y. Ding, "On nominal delay minimization in LUT-based FPGA technology mapping," Integration---The VLSI J., vol. 18, pp. 73--94, 1994.
On Nominal Delay Minimization in LUT-Based FPGA Technology.. - Jason Cong And Self-citation (Cong Ding) (Correct)
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J. Cong and Y. Ding, "On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping," Tech. Report 940022, Computer Science Department, UCLA, USA, May 1994; to appear in INTEGRATION the VLSI Journal.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED.. - Darko Kirovski Member Self-citation (Cong) (Correct)
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J. Cong and Y. Ding, "On nominal delay minimization in LUT-based FPGA technology mapping," in Proc. FPGA, 1995, pp. 82--88.
Optimal FPGA Mapping and Retiming with Efficient Initial State.. - Cong, Wu (1998) (3 citations) Self-citation (Cong) (Correct)
....flipflops. 3 Depending 2 For example, the initial state of FFs on Xilinx XC5200 FPGAs can only be set to 0. 3 For more complex delay models, such as the fanout based nominal delay model, the FPGA mapping of combinational circuits for delay minimization has already been shown to be NP hard [18]. The problem will be even more difficult if layout information is considered. We think, however, the techniques presented in this paper can 2 on the context, we use G to represent both V and E. For a given retiming, the retiming value R(v) of node v is the number of FFs moved backward across v. ....
J. Cong and Y. Ding, "On Nominal Delay Minimization in LUTBased FPGA Technology Mapping," Integration -- the VLSI Journal, vol. 18, pp. 73--94, 1994.
Structural Gate Decomposition for Depth-Optimal Technology.. - Cong, Hwang (1996) (1 citation) Self-citation (Cong) (Correct)
....Among these algorithms, Chortle d guarantees depth optimal technology mapping for simple gate tree networks and FlowMap guarantees depth optimal LUT mapping for general K bounded networks. Following FlowMap, FlowMap r [CoDi94b] and CutMap [CoHw95] further reduce the mapping area, and FlowMap d [CoDi94c] and Edge Map [YaWo94] minimize delay under a more accurate net delay model. Another class of LUT mapping algorithms, such as MIS pga delay [MuSB91] TechMap D [SaTh93] FlowSyn [CoDi93] and ALTO [HuJS96] collapse critical paths followed by delay oriented logic resynthesis. Due to resynthesis, ....
Cong, J. and Y. Ding, "On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping," Integration -- the VLSI Journal, Vol. 18, pp. 73-94, 1994.
On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping - Cong, Ding (1994) (1 citation) Self-citation (Cong Ding) (Correct)
....information, even approximately. In this paper we will also present a simple heuristic to demonstrate the improvement of mapping quality over the depth optimal mapping by taking nominal delay into consideration. Due to page limit most of the proofs will be omitted. Interested readers may refer to [3] for details. 2 Problem Formulation A combinational Boolean network is represented as a directed acyclic graph in which nodes represent logic gates, and edges represent interconnects. A primary input (PI) is represented by a node withoutincoming edge, and a primary output (PO) is represented by ....
....x i ) the variable node of l r j , and call l r j a literal node of x i (or x i ) Such connections are illustrated in Figure 3, and also in Figures 2(a c) in dashed lines) It is clear that the transformation defined above takes O(K(m n) time. Examples of transformations can be found in [3]. Regarding the network N obtained through this transformation, we can see that N is K bounded when K 3, and the only ways of packing more than one node into a K LUT are to pack x i into the K LUT of x i (denoted as pack(x i ) and to pack x i into the K LUT of x i (denoted K 1 L ....
J. Cong and Y. Ding, "On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping," Tech. Report 940022, Computer Science Department, UCLA, USA, May 1994; to appear in INTEGRATION the VLSI Journal.
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