P. Sweazy and A. J. Smith. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In Proceedings of the 13th Annual International Symposium on Computer Architecture, 1986.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....protocols allow only one writer and multiple readers. A write to a shared copy results in all other copies being invalidated before the write can go ahead. Write update, instead of invalidating, updates all copies before the write can go ahead. Most snoopy protocols are variants of the MOESI [187] protocol, so called because of the states uses: Modified, Owner, Exclusive, Shared and Invalid. A number of snoopy protocols have been implemented in various bus based multiprocessors. In the Write once protocol [78] on a read miss, the block comes from another cache if it is in modified state. ....

....memory on each node on a page basis as a globally shared address space. The shared memory pages are kept coherent with a write update protocol. SCI The Scalable Coherent Interface (SCI) 96] is an IEEE standards project (# P1596) which is based on the earlier work of Futurebus standardisation [187]. SCI assumes a large point to point interconnection network for scalability. However, it does not describe a particular topology as it is only an interface. The standard defines a logical and physical layer for up to 64K nodes. A node is notionally a combination of one or more of the following: a ....

P. Sweazy and A. J. Smith. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In Proceedings of the 13th Annual International Symposium on Computer Architecture, 1986.

....in such systems [12] 13] For performance reasons, it is preferable to generate snoop cycles only for shared data rather than all data. Few buses carry the necessary signals to distinguish the different types of accesses. The FutureBus [14] and newer FutureBus [15] 16] are two exceptions [17][18] but they are still relatively unused. The current bus systems (VMEbus, NuBus, Multibus I and II) which do not support cache consistency well, are not likely to be abandoned soon. Furthermore, there are many microprocessors that do not provide hardware coherent caches. The Motorola 68030 and ....

Sweazey, P. and Smith, A.J. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In Proceedings of the 13th Annual International Symposium on Computer Architecture, IEEE Computer Society Press, 2--5 June 1986, pp. 414--423.

....leads to a characterization of SCNF memory models that determines their performance and programmability. We define a generic memory model and a system centric specification for the generic model in terms of this characteristic. Our common characterization for memory models is similar to the MOESI [SwS86] and Dir i [B NB] ASH88] characterizations of cache coherence protocols that unified several seemingly disparate protocols and exposed the design space for more protocols. Our overall approach is to first identify a system centric specification for sequential consistency, and then use it to ....

P. SWEAZEY and A. J. SMITH, A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus, Proc. Thirteenth International Symposium on Computer Architecture, Tokyo, -- -- 158 Japan, June 1986, 414-423.

....in the future, P operations never deadlock. A straightforward implementation maps the P operation onto an indivisible Test And Set instruction: in one indivisible bus cycle, the semaphore value is fetched, tested and overwritten. In an architecture with distributed caches with a MOESI protocol [Sweazy86] (like the Futurebus [Futurebus89] or SCIbasedsystems [SCI92] the TAS operation requires the cache line containing the semaphore to be fetched exclusively. This implies that if two processors in a large architecture are waiting for a busy semaphore, the cache line is transported continuously ....

....unfamiliar with hierarchical caches to read this and the next chapter. The section ends with an overview of the aspects that are not simulated but which are actually part of the Futurebus definition. 6.1. 1 Consistency in flat architectures The Futurebus cache consistency protocol is MOESI like [Sweazy86]. Each cached line of data is in one of the following three states: Exclusive, Shared or Invalid. An Exclusive line of data may be read and written, a Shared line of data is read only, and an Invalid line of data is not here (the same as a cache miss) In a flat lines (with size 2 l bytes) are ....

Paul Sweazy and Alan Jay Smith, "A class of compatible cache consistency protocols and their support by the IEEE Futurebus", Proceedings of the 13th Annual International Symposium on Computer Architecture, pp 414-423, June 1986.

....memory on each node on a page basis as a globally shared address space. The shared memory pages are kept coherent with an update based protocol. SCI The Scalable Coherent Interface (SCI) 51] is an IEEE standards project (# P1596) which is based on the earlier work of Futurebus standardisation [88]. SCI assumes a large point to point interconnection network for the sole purpose of scalability. However it does not describe a particular topology as it is only an interface. At the heart of the SCI project is the distributed directory protocol described earlier. The standard defines a logical ....

P. Sweazy and A. J. Smith. A class of compatible cache consistency protocols and their support by the ieee futurebus. In Proceedings of the 13th Annual International Symposium on Computer Architecture, 1986.

....and a unified L2 cache (Figure 3) All caches follow the write allocate, write back policy. Main memory may be split into multiple banks, interleaved on a cache block basis. If the target bank is busy, the request is put into a bank queue. 3.1.2. Cache Coherence We model caches with a MOESI [5] cache coherence protocol. Processors queue for bus ownership. If a bus transaction is a read request, it is forwarded to the memory if the data is owned by memory, or directly queued to the data bus if another cache can supply the data. All instructions triggering a writeback event on the second ....

P. Sweazy and A. J. Smith. "A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus", In the 13th International Symposium on Computer Architecture, 1986, pp. 414- 423.

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P. Sweazy and A. J. Smith. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In Proceedings of the 13th Annual International Symposium on Computer Architecture, 1986.

No context found.

P. Sweazy and A. J. Smith. A class of compatible cache consistency protocols and their support by the IEEE futurebus. In Proceedings of the 13th Symposium on Computer Architecture, pages 1056--1072, 1986.

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P. Sweazy and A. J. Smith. A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In the 13th Int'l Symp. on Computer Architecture, 1986, pp. 414- 423.

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