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Analysis of Branch Prediction via Data Compression - Chen, Coffey, Mudge (1996) (37 citations) (Correct)
....the full performance of microprocessors. A good branch prediction scheme can increase the performance of a microprocessor by eliminating the instruction fetch stalls in the pipelines. As a result, numerous branch prediction schemes have been proposed and implemented on new microprocessors [MReport95]. Many researchers focus on designing new branch prediction schemes solely based on comparing simulation results. However, very few studies address the theoretical basis behind these prediction schemes. Knowing the theoretical basis helps us to assess how good a prediction scheme is as well as ....
Microprocessor Report, Sebastopol, CA: MicroDesign Resources, March 1995.
Limits to Branch Prediction - Mudge, Chen, Coffey (1996) (Correct)
....because of 0 frequency count transitions. 0 1 0 1 0 1 1 0 1 Input sequence: 00 01 10 11 1 1 0 1 0 2 1 3 next bit frequency January 31, 1996 Limits to Branch Prediction 5 2. 2 Hardware Branch Predictors Most of today s high performance microprocessors support some form of branch prediction [MReport95]. In the next two subsections we will describe some simple methods that are widely used and one advanced method, two level adaptive prediction, that so far has only been used on the Intel Pentium Pro (formerly the P6) 2.2.1 Simple 1 and 2 bit Predictors A 1 bit branch prediction scheme simply ....
Microprocessor Report, Sebastopol, CA: MicroDesign Resources, March 1995.
Tagless Two-level Branch Prediction Schemes - Chen, Lee, Postiff, Mudge (1996) (Correct)
.... predictors [Yeh91] correlation based predictors [Pan92, Yeh92b] and hybrid branch predictors [McFarling92, Chang94] Among different predictors proposed, the two level per address branch predictor has been shown to be one of the best and has been implemented in the Intel Pentium Pro processor [MReport95]. Typically, the two level per address predictor is coupled with a branch target buffer (BTB) through the sharing of common tags [Yeh92a, Calder94] Both components benefit from tags and, thus, cost can be reduced by sharing. In particular, the tags enable high hit rate set associativity design ....
.... Address Per address History Figure 1: Schematics for per address two level branch predictors Tag less Two level Branch Prediction Schemes 4 example, the Intel Pentium Pro employs a two level per address predictor with a 512 entry 4way BHT, where each BHT entry records 4 bit per address history [MReport95]. 3. Tagless per address two level schemes In a typical two level per address scheme, the predictor is coupled with a branch target buffer (BTB) through the sharing of common tags [Yeh92a, Calder94] as shown in Figure 2a. This coupling of predictor and BTB is cost effective in that the predictor ....
Microprocessor Report, Sebastopol, CA: MicroDesign Resources, March 1995.
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