C. Chen and A. Wu, \Microarchitecture Support for Improving the Performance of Load Target Prediction, " Proc. of 30th annual international symposium on Microarchitecture, Triangle Park, NC, Dec. 1997, pp. 228-234. Home/Search Document Not in Database Summary Related Articles Check |
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Compiler-Directed Early Load-Address Generation - Ben-Chung Cheng (6 citations) (Correct)
....the need for new load latency reduction techniques. Various techniques for hiding the latency of load instructions have been investigated in the past. Reducing the load latency by accessing the memory earlier than the normal pipeline stage using early load address generation has been addressed [1][2][3] 4] 5] Similarly, the concept of value prediction [6] 7] has introduced machine models that exceed the limit imposed by data dependences by predicting the outcome values of instructions. One major difference between these two types of techniques is that early load address generation schemes ....
....writes may be necessary. This approach is capable of providing the loaded data at the beginning of the execution (EXE) stage if the load uses register offset addressing mode, or at the beginning of the memory (MEM) stage if the load uses register register addressing mode. Chen and Wu [2] proposed another early address calculation scheme with the stride detection capability. In their scheme instruction predecode is avoided, but multi casting writes are still required. However, since the estimated stride is added in the early address calculation path, it delays the address ....
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C. Chen and A. Wu, "Microarchitecture support for improving the performance of load target prediction," in Proceedings of the 30th Annual International Symposium on Microarchitecture, pp. 228--234, December 1997.
Direct Load: Dependence-Linked Dataflow Resolution of.. - Chung, Zhang, Peir.. (Correct)
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C. Chen and A. Wu, \Microarchitecture Support for Improving the Performance of Load Target Prediction, " Proc. of 30th annual international symposium on Microarchitecture, Triangle Park, NC, Dec. 1997, pp. 228-234.
Symbolic Cache: Fast Memory Access Based on Program Syntax.. - Ma, Peir, Peng, Lai (Correct)
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C. Chen and A. Wu, "Microarchitecture Support for Improving the Performance of Load Target Prediction, " Proc. of 30th annual international symposium on Microarchitecture, Triangle Park, NC, Dec. 1997, pp. 228--234.
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