F. Balarin and A. Sangiovanni-Vincentelli. A verification strategy for timingconstrained systems. In Proceedings of the Fourth Workshop on ComputerAided Verification, pages 148--163, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a case study involving timing properties of the Ethernet protocol, as formally specified by Weinberg and Zuck [22] Previous attempts at verifying this protocol either abstracted away from timing information, or used drastically simpler models. Related work Alur et al. 3] and Balarin et al. [4, 5] describe approximation algorithms which use a different methodology from ours. Their approach assumes that not many timing constraints in the system are necessary for its correct operation. They initially attempt to verify the system based only on logical constraints. Additional untimed processes ....

F. Balarin and A.L. Sangiovanni-Vincentelli. A verification strategy for timing constrained systems. In Proc. of 4th CAV, LNCS 663, Springer-Verlag, 1993.

....However, condition (3) prohibits such a model in the class of decidable Rectangular Automata. A significant shortcoming of automata based verification algorithms is that of state space explosion. To overcome this limitation, techniques such as step wise refinement of the state space (see Balarin [3]) or syntactic model checking (see Henzinger [12] are employed. 1.4 Some Salient Concepts A few of the ideas that we have developed for hybrid control seem useful for other fields as well. These ideas are captured in our definition of control strategy, three way partitioning of controls, and ....

F. Balarin and A. Sangiovanni-Vincentelli. A Verification strategy for timing-constrained systems. In Proc. 4th Workshop Computer-Aided Verification, Lecture Notes in Computer Science 663, Springer-Verlag, 1992.

....that B 1 is more restrictive than B 0 ) To construct B 1 , the original B is simplified as much as possible preserving the inconsistency of r. This is done in a heuristic manner as described in [AIKY95] Alternative schemes of approximations for timing verification are studied in [Won94] and [BS92] Fictitious Clock Approximation The semantics of asynchronous S R models requires that nonzero amount of time is spent in stable states. Let us relax this assumption: a fictitious clock timing assignment for a chain r of an asynchronous model M is a sequence t 0 ; t 1 ; of real valued ....

F. Balarin and A. Sangiovanni-Vincentelli. A verification strategy for timingconstrained systems. In Proceedings of the Fourth Workshop on ComputerAided Verification, LNCS 663, pages 151--163. Springer-Verlag, 1992.

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F. Balarin and A. Sangiovanni-Vincentelli. A verification strategy for timingconstrained systems. In Proceedings of the Fourth Workshop on ComputerAided Verification, pages 148--163, 1992.

....given arithmetic function (see Bryant [83] The timing verification problem for sequential systems, on the other hand, still needs to be formulated in a way that permits the solution of practical problems in a reasonable amount of space and time. One possibility, proposed almost simultaneously by [84] and [85] is to incrementally add timing constraints to an initially untimed model, rather than immediately building the full blown timed automaton. This addition should be done iteratively, to gradually eliminate all false violations of the desired properties due to the fact that some timing ....

F. Balarin and A. Sangiovanni-Vincentelli, "A verification strategy for timing-constrained systems," in Proc. of the Fourth Workshop on Computer-Aided Verification, 1992, pp. 148--163.

....arithmetic function (see Bryant [BC95] The timing verification problem for sequential systems, on the other hand, still needs to be formulated in a way that permits the solution of practical problems in a reasonable amount of space and time. One possibility, proposed almost simultaneously by [BSV92] and [AIKY93] is to incrementally add timing constraints to an initially untimed model, rather than immediately building the full blown timed automaton. This addition should be done iteratively, to gradually eliminate all false violations of the desired properties due to the fact that some ....

F. Balarin and A. Sangiovanni-Vincentelli. A verification strategy for timing-constrained systems. In Proceedings of the Fourth Workshop on Computer-Aided Verification, pages 148--163, 1992.

....such as COSPAN [HK87] is a major obstacle to the extensive application of formal verification techniques to real industrial designs. Reduction techniques are being proposed to cope with this problem. Automatic techniques have been proposed to reduce the complexity of CTL model checking [CSSVB92, BSV92] Non automatic techniques that make use of abstraction, like the one proposed by Kurshan [Kur90] to verify regular properties and the one proposed by Grumberg et al. [DLG92] to perform model checking using the restricted temporal logic CTL , seem powerful. However, their effectiveness depends ....

....while for the hardware timer we need to count 5 and 10 seconds. Immediately we see a state explosion problem. As an experiment, we formulate this seat belt design into a network of N F as in[CGH 93] We then use iterative method for quantitative real time verification as proposed in [BSV92] to verify the property Alarm will not be on forever as described earlier. The verification is allowed to run overnight on a DEC Alpha machine and only intermediate result is obtained. The size of the representation simply grows too large for the verification algorithm to reach its conclusion. ....

F. Balarin and A. Sangiovanni-Vincentelli. A verification strategy for timingconstrained systems. In Proceedings of the Fourth Workshop on Computer-Aided Verification, pages 148--163, 1992.

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