William J. Dally, Larry R. Dennison, David Harris, Kinhong Kan, and Thucydides Xanthopoulos. Architecture and Implementation of the Reliable Router. In Proceedings of 2nd Hot Interconnects Symposium, August 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....servers makes also necessary to provide QoS guarantees within these systems. But the router technologies developed for highspeed multiprocessor interconnection networks or high performance local system area networks (LANs SANs) were optimized for providing low latency to best effort traffic [9][10] These networks are not designed to permit concurrent guarantees of communication performance to multiple applications. For example, nowadays available commercial SAN LAN fabrics such as IBM SP2 [11] Myricom Myrinet [10] HAL Mercury [12] or Tandem ServerNet [13] are not designed to ....

W.J. Dally et al., "Architecture and implementation of the Reliable Router," in Hot Interconnects II, 1994.

....Forward Error Recovery. FER schemes use redundant hardware to mask faults. For example, redundant processors [4, 26, 27, 45] or redundant threads within a processor [42] can be used to mask processor faults. Redundant paths through adaptive networks allow packets to be routed around faults [12, 14]. The Intel 432 [27] uses replication of commodity parts to achieve a range of fault tolerance needs. The Stratus [45] computer system uses pair and spare processors, and the Tandem S2 [26] uses triply modular redundant (TMR) processors, for masking faults. Slipstream [42] is a lighter weight ....

W. J. Dally, L. R. Dennison, D. Harris, K. Kan, and T. Xanthopoulos. Architecture and Implementation of the Reliable Router. In Proceedings of 2nd Hot Interconnects Symposium, Aug. 1994.

....multimedia flows but also traditional best effort traffic generated by conventional applications. Traditional router technology developed for high speed multiprocessor interconnection networks or high performance local area networks (LANs) are optimized for low latency for besteffort traffic [6][7]. These networks are not designed to permit concurrent guarantees of communication performance for multiple applications. The recently proposed InfiniBand SM architecture [8] 9] an attempt for high performance LAN SAN interconnection devised by a consortium of computing industry s leaders ....

....tolerate well latency. C. Switch Organization In most routers the internal switch fabric is implemented as a crossbar. Crossbars can be multiplexed, partially multiplexed or fully demultiplexed [34] depending on the number of ports. Although some routers use a fully demultiplexed crossbar [7], with as many ports as virtual channels, this organization becomes prohibitive when the number of virtual channels is large. Even for a relatively small number of virtual channels, some commercial routers use a multiplexed crossbar [36] The MMR internal switch fabric is a multiplexed crossbar, ....

W.J. Dally et al., "Architecture and implementation of the Reliable Router," in Hot Interconnects II, 1994.

....by the packaging technology, the increase in the dimensionality of a network will decrease the number of wires and thus the bandwidth of a single physical channel. Routers designed for low dimensional k ary n cube networks have physical channels that typically are 8 bitdata to 16 bit data wide [2] [3] [8] 9] 10] In this study, I am proposing a new network topology, called k ary m way network, which is based on the concept of m way channels. The idea of an m way channel is that a maximum number, m, of routers and processors can link directly to it, and hence share the same physical channel. ....

Dally W., et al., Architecture and implementation of the Reliable Router, Proceedings of Hot Interconnects Symposium II, August 1994.

....in recent parallel computers include two and three dimensional meshes and tori. The 2D and 3D interconnection topologies can be found in Intel Paragon [Paragon 91] Stanford DASH [Lenoski 92] Stanford FLASH [Kushkin 94] MIT Alewife [Agarwal 90] MIT J Machine [Noakes 93] MIT Reliable Router [Dally 94] Cray T3D [Oed 93] and Cray T3E [ScottThorson 96] Other popular topologies that are less commonly used are the hypercube and the fat tree. The architecture of a generic wormhole router [Duato 97] is shown in Figure 1. It includes input and or output buffers for storing flits (flow control ....

....pins, a router can be designed to interface physical channels that are 128 bit data wide. This is 8 times the width of physical channels used in state of the art wormhole routers, such as the Intel Teraflops router [Carbonaro 96] the Cray T3E router [ScottThorson 96] and the MIT Reliable Router [Dally 94] With extrawide channels, a network can achieve higher throughput and lower message latency. Proceedings of the ISCA 12 th International Conference on Parallel and Distributed Computing Systems 508 advantage of the multiway channel concept is that a router can be designed to operate under ....

W. J. Dally, et al., "Architecture and implementation of the Reliable Router", Proceedings of Hot Interconnects Symposium II, August 1994.

....of allowing the existence of cyclic dependencies between channels while providing some escape paths to avoid deadlock [13, 14] The resulting routing algorithms are more flexible, usually increasing performance. As a consequence, some recent router implementations like the MIT Reliable Router [10, 11] and the Cray T3E router [30] are based on these techniques, implementing escape paths as dedicated virtual channels. Additionally, there has been a considerable interest on these issues. Several researchers developed alternative theories of deadlock avoidance, proposing sufficient conditions [1, ....

W. J. Dally, L. R. Dennison, D. Harris, K. Kan and T. Xanthopoulos, "Architecture and implementation of the Reliable Router," in Proceedings of Hot Interconnects II, August 1994.

....a flow control signal; hence, the receiving node should either have enough buffer storage for transit packets or otherwise it must send flow control signals in advance of its buffers becoming full. An example of a router that incorporates receiver initiated blocking is the Reliable Router from MIT [19]. It asserts or deasserts a clear to send signal depending on whether there is enough buffer space to receive the next flit. An example of a router that uses sender initiated blocking is the arctic routing chip developed at MIT [8] Valved Routing has been proposed recently as a new back pressure ....

....to enter into bulk mode issues a bulk mode request to the destination processor (receiver) and if granted, the sender can send more than one packet per acknowledgment. 7. 2 Reliable Router MIT s Reliable Router (RR) supports adaptive wormhole routing for both performance and reliability purposes [19]. It was targeted to two dimensional mesh networks and was designed to run at 100 MHz with a link bandwidth of 3.2 Gbit sec. Reliable Router is unique in that it uses a separate virtual network for minimal 26 Delta G. Ravindran and M. Stumm adaptive routing to improve throughput and is also ....

W. J. Dally, L. R. Dennison, D. Harris, K. Kan, and T. Xanthopoulos, "Architecture and implementation of the reliable router," Proc. of Hot Interconnects II, August 1994.

....a flow control signal; hence, the receiving node should either have enough buffer storage for transit packets or otherwise it must send flow control signals in advance of its buffers becoming full. An example of a router that incorporates receiver initiated blocking is the Reliable Router from MIT [22]. It asserts or deasserts a clear to send signal depending on whether there is enough buffer space to receive the next flit. An example of a router that uses sender initiated blocking is the arctic routing chip, also developed at MIT [8] End to end flow control between the source and destination ....

....virtual channel is dictated by the routing algorithm; Otherwise, another allocation scheme is used or any free virtual channel associated with the physical channel is chosen. Hardware support for static virtual channels require status registers at the transmitting and the receiving side of a node [19, 22]. The transmitting node contains a status register for each virtual channel on the corresponding receiving node. The status register normally includes a bit to indicate whether the virtual channel is active or idle and a count of the number of free virtual channel buffers. The active idle bit is ....

W. J. Dally, L. R. Dennison, D. Harris, K. Kan, and T. Xanthopoulos, "Architecture and implementation of the reliable router," Proc. of Hot Interconnects II, August 1994.

....it has to participate in the link level protocol of the network, behaving much like a port in a network switch. Link level protocol covers issues like how the beginning and end of a packet is indicated, and flow control strategy to deal with possible buffer over run problems. In some networks [25, 33], it also includes link level error recovery. This part of the NIU also deals with signal encoding (e.g. Manchester encoding to improve reliability) and the actual electrical levels used in signaling. Data transported over the network has to conform to some format specified by the network. For ....

W. J. Dally, L. R. Dennison, D. Harris, K. Kan, and T. Xanthopoulos. Architecture and Implementation of the Reliable Router. In Proceedings of the Hot Interconnects II, pages 122--133, Aug. 1994.

....each way. The remaining 37 pins carry signals in both directions simultaneously [51] Using both phases on the clock, two phits are transfered every cycle in each direction. To tolerate clock phase differences across routers, the inter chip interface employs a mesochronous technique adapted from [52]. The system clock signal is assumed to be identical throughout the M Machine, except for fixed phase differences due to varying distribution distances. SCLK QCLK RCLK LCLK (case 1) LCLK (case 2) RD QD SD LD sampled off QD LD sample off SD ph0 ph1 unreliable region Figure 4 11: Mesochronous ....

William J. Dally, Larry Dennison, David Harris, Kinhong Kan, Thucydides Xanthopoulos, "Architecture and Implementation of the Reliable Router", in Proceedings of Hot Interconnects, 1004. pp. 122--133.

....control or handshaking signals are used, allowing true undirectional signalling between transmitter and receiver. Application areas include communication networks in parallel computers, and general communication network repeaters, hubs, bridges, and routers. 1: Introduction The Reliable Router [1] project at MIT is developing a VLSI communications chip for use in large parallel computers. The research goals of the project have been on exploring mechanisms to aid in the design of large, high performance, reliable systems. One of the many problems facing the designer of a large digital ....

W.J. Dally, L.R. Dennison, D. Harris, K. Kan, T. Xanthopoulos, "Architecture and Implementation of the Reliable Router," In Hot Interconnects II: 1994 Symposium Record.

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William J. Dally, Larry R. Dennison, David Harris, Kinhong Kan, and Thucydides Xanthopoulos. Architecture and Implementation of the Reliable Router. In Proceedings of 2nd Hot Interconnects Symposium, August 1994.

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