Motorola Corporation. MC88100 RISC Microprocessor User's Manual, 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....[76] 97] 102] The dependency checking complexity has also been reduced by restricting the type and number of dependency checks performed. One example of a simpler dependency structure is a register scoreboard, first used in the CDC 6600 [175] and more recently in the Motorola 88000 processor [117]. In a scoreboard, a bit is associated with each register. A register is marked busy if it is the target register for an instruction currently being executed. Instructions are blocked from execution if any of their registers are marked busy. Execution of other instructions is allowed to proceed. ....

Motorola, MC 88100 RISC Microprocessor User's Manual, Prentice Hall, Englewood Cliffs, New Jersey, 1989.

....the Intel NX message passing run time system. This communication model was replaced by the Cranium application programmer interface. 5.1. 1 Talisman s timing model The timing model used in Talisman is based on a black box cost analysis of each of the major structural units in the Motorola 88100 [72]. Talisman maintains models of the memory system, the instruction cache and data cache, the translation lookaside buffer, the execution pipeline and the write buffer (a three element FIFO) The timing model in Talisman was calibrated against the Meerkat 1 hardware prototype [35] Through the use ....

....four 90 MHz hyperSPARC processors, each rated at 100 SPECint92. The extra processors contribute little to improving host execution latency but make it possible to run several independent simulations concurrently. The simulated target architecture is based on a 20 MHz Motorola 88100 processor [72] and a pair of 88200 cache memory units [77] One 88200 is used as an instruction cache and another as a data cache; they complement the 88100 s separate instruction and data busses. This separation is also known as a Harvard architecture. The 88200 contains 16K bytes of data organized as 16 ....

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Motorola Inc. The MC88100 RISC Microprocessor User's Manual, second edition. Prentice-Hall, Englewood Cliffs NJ, 1990.

....interrupt masking has been efficient, requiring only a few cycles. Unfortunately, the time required to modify the hardware interrupt level has not scaled with processor speed improvements. In pipelined processors, writing the processor interrupt mask typically requires a pipeline flush [13, 14]. In superscalar systems, interrupt level manipulations require scalar instruction issue, further limiting performance [15] Many recent RISC CPU implementations provide only a part of the interrupt mask logic on the processor package, with the remainder of interrupt masking implemented by ....

.... systems, interrupt level manipulations require scalar instruction issue, further limiting performance [15] Many recent RISC CPU implementations provide only a part of the interrupt mask logic on the processor package, with the remainder of interrupt masking implemented by off processor hardware [13, 14]. For these systems, interrupt masking is a three step process: 1) disable processor interrupts, 2) write the off chip mask register(s) and 3) finally reenable processor interrupts. The first stage requires a pipeline flush, and the second stage requires a potentially expensive off chip access. ....

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Motorola. MC88100 RISC Microprocessor User's Manual. Prentice Hall, Englewood Cliffs, NJ, 1990.

....set for a RISC processor can be a complex task [9, 8, 10] Rather than attempt to design a new instruction set from scratch, an instruction set from an existing commercial RISC processor was adapted. Much of the Fred instruction set is taken directly from the Motorola 88100 instruction set [12]. However, Fred does not implement all the 88100 instructions, and several of Fred s instructions do not correspond to any instructions of the 88100. The instructions, and the functional units that execute them, are shown in Figure 3. Logic Bitfield Arithmetic Memory Branch Control and clr add ....

Motorola. MC88100 RISC Microprocessor User's Manual. Prentice Hall, Englewood Cliffs, New Jersey 07632, second edition, 1990.

....Figure 4.1 Fred block diagram 16 4.3. Instruction Set Choosing an instruction set for a RISC processor can be a complex task [21,20,23] Rather than attempt to design a new instruction set from scratch, much of the Fred instruction set was taken directly from the Motorola 88100 instruction set [26]. However, Fred does not implement all of the 88100 instructions, and several of Fred s instructions do not correspond to any instructions of the 88100. Fred s instruction format is triadic, where most instructions specify two source registers as operands and one destination register for the ....

Motorola, MC88100 RISC Microprocessor User's Manual. Englewood Cliffs, New Jersey 07632: Prentice Hall, 2nd ed., 1990.

....the time to change address spaces in the hardware. This does not include the time to find another process to run. Our measurements examined a CISC implementation, the VAXstation 3200 (11.1 MHz CVAX [Leonard 87] and four RISC implementations: the Tektronix XD88 01 (20 MHz Motorola 88000 [Mot 88a, Mot 88b] DECstation 3100 (16.6 MHz MIPS R2000 [Kane 87] DECstation 5000 200 (25 MHz MIPS R3000 1 ) and SPARCstation 1 (25 MHz Sun SPARC [Sun 87, Cyp 90] For brevity, our tables list the architecture or microprocessor names, rather than the system names, although performance is of ....

Motorola, Inc., Phoenix, AZ. MCS 88100 RISC Microprocessor User's Manual, 1988.

.... = 1, then any instruction level concurrency that is exploited increases the utilization beyond 1 since proc = To achieve higher clock rates, modern microprocessors use increasing degrees of pipelining, resulting in higher (3 to 5 cycle floating point latencies are not uncommon) [29, 24, 13]) Memory accesses also incur long latencies, especially in multiprocessors where cache miss rates tend to be higher due to sharing and main memory accesses must traverse multistage networks. In order to maintain good utilization , the exploited concurrency proc must equal for the si ....

....clock cycle, on average. Note that in most superscalar and VLIW processors, there are some restrictions on the combination of instructions that can be issued in a single clock cycle because there are a limited number of functional units of each type (e.g. one integer and one floating point unit [29, 13]) Therefore, fi is generally less than the peak theoretical issue rate, and depends on the instruction mix in the region of code being executed, since there is always one critical resource that is 100 utilized while other functional units receive a smaller fraction of instructions. For example, ....

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Motorola, Inc., Englewood Cliffs, New Jersey 07632. MC88100 RISC Microprocessor User's Manual, second edition, 1989. ISBN 0-13-567090-X.

....latency. In software controlled cache prefetching, the CPU executes a special prefetch instruction for data that is to be loaded at some point in the near future. In the best case, the data arrives at the cache before it is needed by the CPU, and the CPU sees its load as a hit. Lockup free caches[17, 21, 25, 27], which allow the CPU to continue execution during the prefetch, hide the prefetch latency from the CPU. In this paper we address the issue of prefetching in bus based, shared memory multiprocessors. The goal of our work is to gauge its impact on the performance of these architectures and to ....

Motorola. MC88100 RISC Microprocessor User's Manual. Prentice Hall, 1990.

....generator that includes code selection, instruction scheduling and global register allocation. Marion was designed specifically for uniprocessor RISCs that contain multiple functional units and multi cycle operations. It has been used successfully to produce code generators for the Motorola 88000 [Mot88] the MIPS R2000 [Kan87] and the Intel i860 [Int89] The 88000 and the R2000 are traditional RISC machines that are more similar than different; in contrast, the i860 can issue two instructions per cycle and has explicitly advanced floating point pipelines, making it an extremely challenging ....

....5 div (float) 12 div (double) 19 The FPU supports single and double precision floating point operations, including multiply and divide. Conversions between integer and floats are also handled by the FPU. Latencies are shown in Table 2.1. 2. 2 Motorola 88000 The Motorola 88000 architecture [Mot88] has 32 general purpose registers that are used for both integer and floating point values. Double precision floats use register pairs. Register r0 is hardwired to 0. The CPU has a 4 stage instruction pipeline. All integer operations, except multiply and divide, use the ALU stage for one cycle. ....

Motorola, Inc. MC88100 RISC Microprocessor User's Manual, 1988.

....memory latencies during instruction scheduling. Two architectural innovations make it worthwhile to reconsider how to schedule behind load instructions. The first is processor designs that do not stall on unsatisfied load references (called nonblocking loads) through the use of lockup free caches[19, 20, 16, 13], multiple hardware contexts[2, 1] or an instruction lookahead scheme[2] Nonblocking loads allow a processor to continue executing other instructions while a load is in progress. Although the design requires more complex hardware, more instruction level parallelism can be exploited, and therefore ....

....architectures. The first has a data cache. A load instruction s data is returned after 2 cycles on a cache hit and either 5 or 10 cycles on a cache miss. The model represents a typical workstationclass risc processor that implements nonblocking load instructions, such as the Motorola 88000 series[16]. It is simulated with cache hit rates of 80 and 95 , modeling first level caches of 4K and 32K bytes, respectively[11] Four configurations are modeled, and are referred to as Lhr(hl,ml) where Lhr stands for lockup free caches with a hit rate of hr, and hl and ml are hit and miss latencies, ....

Motorola. MC88100 RISC Microprocessor User's Manual. Prentice Hall, 1990.

....interrupt masking has been efficient, requiring only a few cycles. Unfortunately, the time required to modify the hardware interrupt level has not scaled with processor speed improvements. In pipelined processors, writing the processor interrupt mask typically requires a pipeline flush [Motorola 90, DEC 92] In superscalar systems, interrupt level manipulations require scalar instruction issue, further limiting performance [Sites 92] Many recent RISCCPU implementations provide only a part of the interrupt mask logic on the processor package, with the remainder of interrupt masking ....

.... interrupt level manipulations require scalar instruction issue, further limiting performance [Sites 92] Many recent RISCCPU implementations provide only a part of the interrupt mask logic on the processor package, with the remainder of interrupt masking implemented by off processor hardware [Motorola 90, DEC 92] For these systems, interrupt masking is a three step process: 1) disable processor interrupts, 2) write the off chip mask register(s) and 3) finally re enable processor interrupts. The first stage requires a pipeline flush, and the second stage requires a potentially expensive off chip ....

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Motorola. MC88100 RISC Microprocessor User's Manual. Prentice Hall, Englewood Cliffs, NJ, 1990.

....gain insight in the issues of performance, efficiency of design, packaging considerations, and suitability from the software point of view. The prototype consists of 32 PMs organized into 8 stations of four PMs each. Each station may contain up to 8 PMs. Each PM contains a Motorola 88100 processor [14], up to 256K of cache, 16 MBytes of memory, a station bus interface (SBI) and I O interfaces that include serial, SCSI, and Ethernet ports. Most of the PM logic has been implemented using PAL chips, which uses up much real estate on the printed circuit boards and has caused some constraints. For ....

Motorola Inc. MC88100 RISC microprocessor User's Manual, 1988.

.... The CDC6600 machine featured a register scoreboard which allowed instructions to be issued before previous instructions were completed, and allowed pipelined instructions to complete out of order [105] Scoreboards can be found in modern pipelined RISC microprocessors, such as the MC88000 family [43, 75]. Tomasulo s common data bus architecture featured similar capabilities and, in addition, implemented dynamic register renaming, allowing multiple instances of a given instruction to execute simultaneously [106] A similar approach based on an instruction dispatch stack was proposed later by ....

.... ( 1) then any instruction level concurrency that is exploited increases the utilization beyond 1 since proc = To achieve higher clock rates, modern microprocessors use increasing degrees of pipelining, resulting in higher (3 to 6 cycle floating point latencies are not uncommon) [75, 54, 33]) Memory accesses also incur long latencies, especially in multiprocessors where cache miss rates tend to be higher due to sharing and main memory accesses must traverse multistage networks. To maintain good utilization , the exploited concurrency proc must equal for the SI processor, and ....

[Article contains additional citation context not shown here]

Motorola, Inc., Englewood Cliffs, New Jersey 07632. MC88100 RISC Microprocessor User's Manual, second edition, 1989. ISBN 0-13-567090-X.

No context found.

Motorola, Inc., MC88100 RISC Microprocessor User's Manual, second edition, ISBN 0-13-567090-X, Prentice-Hall, 1989

No context found.

Motorola Corporation. MC88100 RISC Microprocessor User's Manual, 1988.

No context found.

Motorola. MC88100 RISC Microprocessor User's Manual. Englewood Cliffs, NJ, Prentice Hall, 1990.

No context found.

Motorola Inc., MC88100 RISC Microprocessor User's Manual, Motorola, 1988.

No context found.

Motorola. MC88100 RISC Microprocessor User's Manual. Englewood Cliffs, NJ, Prentice Hall, 1990.

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