A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....on a specific computer, determine the portions of the code or the data structures that result in a large fraction of the cache misses, and then optimize these code segments and or data structures. Trace driven simulations have also been used to develop analytical models of cache behavior. See [4, 15, 19, 22 24], for example, for some ways in which trace driven simulators have been used in cache performance enhancement studies. La Maxca and Ladner [13] develop a model for a single level direct mapped cache. They use this model to analyze the performance of binary heaps and cache aligned d heaps. LaMarca ....

A. Aggarwal, M. Horowitz, and Hennessey. An analytical cache model. The ACM Transactions on Computer Systems, 7(2):184-215, 1989.

....Partitioning can eliminate the problem. 6. Related Work Several early investigations of the effects of context switches use analytical models. Thiebaut and Stone [20] modeled the amount of additional misses caused by context switches for set associative caches. Agarwal, Horowitz and Hennessy [1] also included the effect of conflicts between processes in their analytical cache model and showed that inter process conflicts are noticeable for a mid range 10 0 10 1 10 2 10 3 10 4 10 5 10 6 0.02 0.025 0.03 0.035 0.04 0.045 0.05 Reference per Time Quantum Miss rate Normal ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2), May 1989.

....acceses. Since we have no information about the distribution of the recurrent accesses among the new footprint and the recurrent footprint, we will assume that it is distributed uniformly (this assumption is accepted in similar studies of other models that appear in the literature such as [agar89]) In the following discussion we will evaluate this distribution. Let p(n) denote the ratio of the amount of new footprint lines out of the overall footprint lines accumulated in processor 2 s cache (for T n m ) p(n) can be expressed by equation 3.15: p(n) K n K T K n ....

A. Agarwal, M. Horowitz and J. Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, vol. 7, no. 2, May 1989.

....numerous special purpose memory models have been developed. Hardware designers use trace driven simulations to learn how to develop better hardware caches. Such models and simulations are very realistic, but rather difficult as a basis for mathematical algorithm analysis. 1 1 Agarwal et al. [2] extract statistical information of traces and develop a more tractable model, yet mainly intended for hardware designers. 4 CHAPTER 2. MODULAR BLOCK CACHING 5 Several models have been proposed to handle two level memories and I O complexity [5, 17, 23, 28] whereas only few models for ....

A. Agarwal, M. Horowitz, J. Hennessy, An Analytical Cache Model. ACM Transactions of Computer Systems, 7:2 (1989), pp. 185--215.

....al. 91] added to the list of sampling techniques evaluated here (this is the most accurate technique and should be included for completeness) A more major addition will evaluate the effectiveness of trace sampling in the estimation of parameters for analytical cache models like those of Agarwal [Agarwal et al. 89] Finally, the limits of sampling will be evaluated by considering sampling measures beyond the cache memory hierarchy. In particular, we will consider the accuracy of sampling branch prediction behavior for the same set of Windows NT desktop application traces. ....

Agarwal, A., Horowitz, M., and Hennessy, J. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184-- 215, May 1989.

.... over a large variety of applications, relying on benchmark suites such as SPEC [16] The impact of cache memory parameters on program behavior has been widely studied in the past [14] Techniques for modeling cache features and utilizing them in program transformations have been reported in [1, 19]. However, individual applications have widely varying memory characteristics, and in an application specific IC, it is essential to optimize performance by tailoring the on chip memory organization to the requirements of a given application. We address this issue in this paper. In high level ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

....of architectures now) a complete simulation is almost out of reach. The performance of an architecture can also be estimated through analytical models. They can give first estimates about some key parameters of the memory hierarchy. Extended surveys on this subject can be found in [17] and [2]. The main problem in this case is to agree on a mathematical model for the references generated by a program. The model must be analytically tractable and it must represent in a reasonable way the behavior of a program in a memory hierarchy. The independence reference model (IRM) used in the ....

....of the others so that almost no spatial or temporal locality of the references will be represented in this model. Moreover it assumes a fixed length of line and thus does not allow the analysis of the optimal line size. An analytical description of the behavior of a cache has been proposed in [2] where the authors proposed a small set of parameters to evaluate the performance of a cache memory. These parameters include the notion of intrinsic interference (collisions within the cache of the blocks of the same programs) The essential idea is that the behavior of a cache is due to a ....

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Agarwal, A., Horowitz, M., and Hennessy, J. An analytical cache model. ACM Transactions on Computer Systems 7, 2 (May 1989), 184--215.

....An analytical cache model also has the inherent advantage that it helps a designer understand the algorithm and helps uncover possible optimizations. A number of researchers have employed hybrid modeling techniques in which a combination of trace driven simulation and analytical models is used [1, 29]. These techniques compress an address trace into a few key parameters describing an application s behavior, and these are then used to drive an analytical cache model. The difference between the collective analysis framework we present and these techniques is that collective analysis does not ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7:2:184--215, 1989.

....into the dependence of the cache miss rate on program and workload parameters. Analytical models, however, lack the accuracy of either simulation or hardware measurement. Some of the analytical models that have been proposed are by Smith [72] Thiebaut and Stone ( 77] and [78] and Agarwal [2]. Smith fits a continuous curve to the simulation results that he obtained for different line sizes, and derives an empirical model. Thiebaut and Stone [78] present a simple fractal model to predict the miss rate of a workload as a function of the cache size. This model handles only ....

A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

....and miss penalty increases as the line size is increased [174] In a shared memory system, the behaviour of sharing plays an important part in determining the best item size. In particular, increasing the item size beyond a threshold increases the potential for false sharing or ping ponging [5] of data. False sharing occurs when processors share a block or item, but actually reference different parts of the block. False sharing (page thrashing [121] is considered to be a significant drawback in software SVM systems, where the item granularity is much larger (usually a page) ....

A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

....An analytical cache model also has the inherent advantage that it helps a designer understand the algorithm and helps uncover possible optimizations. A number of researchers have employed hybrid modeling techniques in which a combination of trace driven simulation and analytical models is used [1, 35]. These techniques compress an address trace into a few key parameters describing an application s behavior, and these are then used to drive an analytical cache model. The difference between the collective analysis framework we present and these techniques is that collective analysis does not ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7:2:184--215, 1989.

....an analytical model. This feature allows the model to be used in the preprocessing or the compilation step to drive optimizations of the code. Most of the work devoted to analytical modelling focus on predicting the number of cache misses, and do it on codes with regular accesses. In particular [1,23,10] present analytical models which analyze perfect nested loops. For the case of irregular codes, the number of articles on modelling is small as a result of the difficulty for finding general models describing their characteristics. Even so, in this group we can emphasize [8] where the authors ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, 1989.

....investigate what types of caches, for example MRU (most recently used) caches, are not accurately represented by cache characterization surfaces. 3. 3 Cache Simulation Prediction Many researchers have attempted to use analytical models to replace cache simulations with varying degrees of success [32] [33] 34] Most researchers simply show miss rate prediction curves versus miss rates from simulation to validate their models. In addition, the models in [33] and [34] only work for fully associative caches. These models essentially reduce the time necessary to calculate miss rates for one kind ....

....no traces of any signi cant length or accuracy, so synthetic trace generation was the only way to get long, somewhat reasonable traces. Some models created at this time include the Independent Reference Model [20] 21] the Distance and Distance Strings Models [22] 36] the Partial Markov Model [32], and the Stack Model [37] Each of these models has a nite number of input parameters that can either be invented from thin air or pulled from a real trace. More recently, other models have been proposed, such as the Piecewise Independent Stochastic Process Model [38] and the Random Walk Model ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184-215, May 1989.

....one is interested only in a cache of a fixed size and a fixed associativity. Analytical cache models were developed to quickly estimate cache miss ratios. To the best of our knowledge, no analytical cache models have yet been presented that can handle varying set index functions. Agarwal et al. [1] present an analytical model of caches that models the effect of cache parameters, as well as multiprogramming conditions. The model independently models conflict misses by extrapolating the number of conflict misses for one cache to larger cache sizes. Therefore, it models how conflict misses ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transaction on Computer Systems, 7(2):184--215, May 1989.

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Artant Agarwal, Mark Horowitz, and John Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, Vol. 7, No. 2, Pages 184-215, May 1989.

....Finally, Section 5 concludes the paper. 2. RELATED WORK Several early investigations of the effects of context switches use analytical models. Thi ebaut and Stone [20] modeled the amount of additional misses caused by context switches for set associative caches. Agarwal, Horowitz and Hennessy [1] also included the effect of conflicts between processes in their analytical cache model and showed that inter process conflicts are noticeable for a mid range of cache sizes that are large enough to have a considerable number of conflicts but not large enough to hold all the working sets. ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2), May 1989.

....processing. The fact that u(R(x i ) L) is a power function of R(x i ) for fixed L was observed independently by Thiebaut [23, 24] and Kobayashi and MacDougall [11] In [20] the authors show equation (1) to be consistent with data given by Smith [21] and Agarwal, Horowitz and Hennessy [1]. They also demonstrate its accuracy through detailed validation on segments of a 200 millionreference trace of a multiprogrammed IBM 370 MVS workload, consisting of a representative workload of user applications and operating system activity. We use the specific parameters derived by the authors ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

....and the main memory (since no information was written to the main memory from that time on) Thus, by invalidating the contents of the cache and reloading the processor state at that point, we establish consistency in the data content of the cache and the main memory. 2 Cache models, such as [5, 1, 12], indicated the existence of working sets during the executing time of the program. These assume that the miss ratio within the working set can be considered as a constant and only when the program moves from one working set to another, a burst of cache misses can occur. If we assume a uniform ....

A. Agarwal, M. Horowitz, and J. Hennessy, An analytical cache model, ACM Transaction on Computer Systems, May 1989.

....commonly found in modern machines. In direct mapped caches, the data item brought into the cache can only go to one place. The result is that our analyses are both different and likely more useful in practice than cache analyses for fully associative caches [17] There have been several studies [1, 17, 19, 20] that have tried to quantify the cache performance of programs by summarizing or analyzing actual memory access traces. Our work differs from this in that we do not examine the trace of a program, but just the actual algorithm itself. A number of studies have analyzed different memory hierarchy ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, 1989.

....processing. The fact that u(R(x i ) L) is a power function of R(x i ) for fixed L was observed independently by Thiebaut [31, 32] and Kobayashi and MacDougall [16] In [28] the authors show equation (1) to be consistent with data given by Smith [29] and Agarwal, Horowitz and Hennessy [1]. They also demonstrate its accuracy through detailed validation on segments of a 200 millionreference trace of a multiprogrammed IBM 370 MVS workload, consisting of a representative workload of user applications and operating system activity. We use the specific parameters derived by the authors ....

A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

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A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

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A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, 1989.

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A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

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A. Agarwal, M. Horowits, and J. Hennessy. An Analytical Cache Model. ACM Transactions on Computer Systems, 7(2):184--215, May 1989.

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A. Agarwal, M. Horowitz, and J. Hennessy. An analytical cache model. ACM Transactions on Computer Systems, 7(2), May 1989.

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