C. A. Healy, D. B. Whalley, and M. Harmon. Worst-case timing analysis of instruction caches with wrap-around fill. TR 96-111, Florida State University, Department of Computer Science, 1996. 68 69 Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Generalizing Timing Predictions to Set-Associative Caches - Mueller (1996) (7 citations) (Correct)
....The timing analyzer calculates the WCET by constructing a timing tree, traversing paths within each loop level, and propagating this timing information bottom up within the tree. During this traversal, the timing analyzer has to take hardware characteristics into account (e.g. pipelining [8]) and the instruction categorizations have to be interpreted. However, the timing analyzer does not have to take the cache configuration into account. The approach of splitting cache analysis via static cache simulation and timing analysis makes the caching aspects completely transparent to the ....
....could be lifted within the framework of the static cache simulator by bounding the recursion depth [15] The timing analyzer has been extended to support pipeline simulation [7] Current work includes an extension of the pipeline model to support wrap around caches, e. g, for the MicroSparc I [8]. The process of static cache simulation could be further enhanced by providing more detailed information about the control flow of a program. Currently, we are investigating analytical methods and user annotations to support such improvements. 8 Conclusion This paper describes a formal method ....
C. A. Healy, D. B. Whalley, and M. G. Harmon. Worst-case timing analysis of instruction caches with wraparound fill. In IEEE Real-Time Systems Symposium, December 1996. (submitted).
Generalizing Timing Predictions to Set-Associative Caches - Mueller (1996) (7 citations) (Correct)
....The timing analyzer calculates the WCET by constructing a timing tree, traversing paths within each loop level, and propagating this timing information bottom up within the tree. During this traversal, the timing analyzer has to take hardware characteristics into account (e.g. pipelining [9]) and the instruction categorizations have to be interpreted. However, the timing analyzer does not have to take the cache configuration into account. The approach of splitting cache analysis via static cache simulation and timing analysis makes the caching aspects completely transparent to the ....
C. A. Healy, D. B. Whalley, and M. G. Harmon. Worst-case timing analysis of instruction caches with wraparound fill. In IEEE Real-Time Systems Symposium, December 1996. (submitted).
Bounding Worst-Case Data Cache Performance - White (1996) (4 citations) Self-citation (Whalley) (Correct)
....caching. This analysis would result in tighter estimations since the MicroSPARC I does use wrap around fill for both instruction and data caching [25] Wrap around fill analysis for data caching can probably be accomplished in a manner similar to that used for wrap around fill instruction caching [10]. It is currently assumed that each store requires a constant penalty for accessing memory with a writethrough data cache. 53 54 9.3 Write Buffer Another area to be explored is evaluating the effect of the use of a write buffer. The MicroSPARC I actually has a write buffer that can hold the ....
C. A. Healy, D. B. Whalley, and M. Harmon. Worst-case timing analysis of instruction caches with wrap-around fill. TR 96-111, Florida State University, Department of Computer Science, 1996. 68 69
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