L. Nachtergaele, I. Bolsens, and H. De Man. Specification and simulation front-end for hardware synthesis of digital signal processing applications. International Journal in Computer Simulation, Vol. 2, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....at each filter node is noise shaped, with more severe noise shaping occurring at nodes closer to the quantizer. As a consequence, the filter wordlengths can reduce towards the quantizer without a severe increase in baseband noise power. The wordlengths were optimised heuristically using the Silage [10] bit true simulation language, resulting in wordlengths ranging from 26 bits at the first integrator output (I 1 ) to 15 bits at the last integrator output (I 7 ) To prevent excessive internal signal levels, the integrator structure also incorporates shifters before each node which re align the ....

....layout. To overcome this problem the serial to parallel converter and interpolation filter were manually routed to maximize silicon usage, releasing sufficient space to allow the routing tool to layout the main modulator automatically. 4 Performance Bit true simulations using the Silage language [10] and VHDL reveal that the modulator achieves over 18 bit resolution at an average PRF of 352:8 kHz. The baseband response of the modulator with a 1 kHz sinewave at in input level of 0.3 is shown in figure 14. The performance of the implemented modulator shows slight degradation due to analogue ....

L. Nachtergaele, I. Bolsens, and H. De Man. Specification and simulation front-end for hardware synthesis of digital signal processing applications. International Journal in Computer Simulation, Vol. 2, 1992.

.... 2 Multi dimensional data streams Particularly well suited for describing DSP algorithms are applicative languages 1 , that include a stream concept as part of the language semantics (figure 1) Each array access in a Silage source text, such as a[i 1] groups a number of entries, such as a[4] a[5] and a[6] inside a loop (i:5. 7) Each entry of a data structure is located inside the N 1 dimensional stream by its coordinates or index set I = I 0 ; I 1 ; I N ] in a coordinate system E = E 0 ; E 1 ; EN ] By convention, the implicit time dependent index runs along the ....

....In the direction E 0 , the size S 0 is always 1. In practical computations, it is substituted by the time window W 0 , which is equal to the maximum delay value of any entry of the array, incremented by 1. The entries of S are computed by a symbolic simulation of the Silage source text [5]. As all data structures are infinite, only parts of them can be stored in any particular state of the computation. The compiler is responsable for computing which part. The memory management strategy for minimising this relevant part and for organising the data in physical locations, is ....

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L.Nachtergaele, I.Bolsens, H.De Man "A Specification and Simulation Front-end for Hardware Synthesis of Digital Signal Processing Applications," accepted for publication in the Int. Journal of Computer Simulation, Special Issue on Multi-processor Simulation.

....proposed in our own project, as well as links to other approaches are indicated. The design process will be further illustrated with a case study in Sections 4 to 6. ffl Behavioural specification. In the Cathedral environment, use is made of the Silage specification language with its simulator [13]. Silage is based on data flow semantics. In the future, extensions of the specification model are envisioned to include control flow semantics, which are needed to characterise the system control and protocol layer. A similar mix of specification models is intended by Grape [11] and Ptolemy [9] ....

L. Nachtergaele, I. Bolsens, H. De Man, "A specification and simulation front-end for hardware synthesis of digital signal processing applications", International Journal of Computer Simulation (special issue on simulation of highly parallel systems), September 1991.

....signals is not always possible. Background memory size estimation has only recently gained attention in high level synthesis. The first estimation methods are based on symbolic evaluation a scalar oriented technique which consists in enumerating all indexed signals for all index combinations [24]. More recently, novel results have been obtained for the case when the algorithm specification is non procedural. Modifications of the loop hierarchy and the sequence of execution as specified in the source code are used to optimize the storage requirements [36] Retaining only the data flow ....

L. Nachtergaele, I. Bolsens, H. De Man, "Specification and simulation front-end for hardware synthesis of DSP applications," Int. J. in Comp. Simulation, vol. 2, pp. 213-229, 1992.

.... processing, front end telecom and numerical computing systems indicate that many algorithms exhibit a large amount of control flow, including many loops, and multi dimensional signals [3] This is especially so if the applications are described in an applicative way using languages like SILAGE [7]. It leads to a severe memory bottleneck when such algorithms have to be mapped on hardware with traditional synthesis techniques. Indeed, architecture experiments make clear that between 50 and 80 of the area cost in (application specific) architectures for real time multi dimensional signal ....

....all individual operations provides us with complete information concerning the life times of variables or signals. Consequently, a left edge type algorithm is then sufficient. Unfortunately, when describing an algorithm involving M D signals in a non procedural (applicative) language, as SILAGE [7], or equivalently, when a complete optimized ordering of the procedural description was not yet provided by the designer, the problem becomes theoretically untractable. Therefore, a natural way of solving the problem under these constraints is by means of an accurate data flow analysis, preceding ....

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L.Nachtergaele, I.Bolsens, H.De Man, "Specification and simulation front-end for hardware synthesis of digital signal processing applications", Intnl. J. in Computer Simulation, Vol.2, No.2, pp.213--230, 1992.

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