Digital Equipment Corporation. Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....wide path is provided to allow a continuous stream of eight 32 bit instructions from the 64 KB of program RAM to the CPU. The internal data RAM is 64KB in size and is divided into four banks of 16 KB. The CPU provides two data paths to the data memory system. 3. 2 Alpha 21164 The Alpha 21164 [Alpha 21164, 1997] is a 64 bit RISC architecture which is capable of executing four instructions per cycle at a clock rate of 500 MHz. The architecture of the Alpha 21164 is in order and can initiate the execution of two integer and two floating point operations per cycle. Speculative execution is made possible in ....

....of the 21164. Indeed, in Figure 10, the number of clock cycles is larger for the Alpha 21164 than for the C67 for the highest optimized version of snake (version 10) It is also interesting to make a note on the power consumption of both microprocessors. The Alpha 21164 consumes 41W max power [Alpha 21164, 1997]. The C67 on the other hand, consumes at least a factor 10 less power under a worst case sce nario [SPRA486B, 1999] Since the execution times are comparable on both microprocessors, we can expect that executing the algorithm on the C67 will be far more energy efficient than executing the ....

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Digital Equipment Corporation. Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual.

....the fetching mechanism. This redirection causes breaks in the, otherwise linear, fetching of instructions and as a consequence, bubbles are introduced in the pipeline execution: the pipeline is not fed with new instructions for some cycles. For example, on the Digital Alpha 21164 processor [35], the outcome of a conditional branch is not known until the sixth stage of the pipeline, while the next fetch address should be known after the rst stage to maintain execution. Reordering of basic blocks and code in general can optimize the execution of programs by decreasing the number of ....

Digital Equipment Corporation. Digital Semiconductor 21146 Alpha Microprocessor - Hardware Reference Manual, preliminary ed. Maynard, Massachusetts, February 1997.

....[4] SimOS Alpha is a full system simulation environment that simulates the hardware components of Alpha based multiprocessors (processors, MMU, caches, disks, console) in enough detail to run Alpha system software. Specifically, SimOS Alpha models the micro architecture of an Alpha processor [10] and runs essentially unmodified versions of Tru64 Unix 4.0 and PALcode. The ability to simulate both user and system code under SimOS Alpha is essential given the rich level of system interactions exhibited by commercial workloads. For example, for the OLTP runs in this study, the kernel ....

Digital Equipment Corporation. Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual. March 1996.

....ADDRESS HIT ABORT Figure 1. RPLB architecture synthesized with Synopsis Design Compiler using 0.35 micron library. technology. The most important of these were that the synthesis used an LRU replacement algorithm as contrasted to the Not Last Used algorithm used by DEC in the Alpha TLB [26]; a generic RPLB was synthesized rather than three separate RPLBs designed specifically for protection of instruction; data and domain switching accesses, and CAD tools, library elements and custom techniques available to DEC [27] were not available to the synthesis. More details can be found in ....

Digital Equipment Corporation, Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual, Order Number: EC-QP99B-TE, January 1997.

....errors. Higher values, however, indicate that some of the array references are not implemented as loads or stores, but as register accesses. The analysis clearly shows that for the 32 32 and 64 64 grids, which both t completely into the L2 cache of the memory hierarchy (see Figure 1, [8]) the algorithm can access all of the data from L1 and L2. But as soon as the data does no longer t into L2, a high fraction of the data must be retrieved from L3. An analogous e ect can be observed for problems which are too large to t entirely into L3 (grid size 512 512) In this case, a ....

Digital Equipment Corporation, Maynard, Massachusetts. Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual, 1997. Order Number: EC-QP99B-TE.

....page size in the primary TLB and have auxiliary hardware to support large pages. Processor Primary TLB Auxiliary TLB TLB size Page size(s) TLB size Page size(s) IBM PowerPC 603e [IBM 95] 64I 64D 4 KB 4I 4D 128 KB, 256 KB, 256 MB Intel Pentium Pro [Int 97] 32I 64D 4 KB 4I 8D 4 MB Alpha 21164 [Dig 97] 48I 64D 8 KB, 64 KB, 512 KB, 4 MB not applicable HP PA 8000 [Hunt 95] 96 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 8 MB not applicable MIPS R10000 [Heinrich 96] 64 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 8 MB not applicable UltraSparc II [Sun 97] 64I 64D 8 KB, 64 KB, 512 KB, 4 MB not applicable ....

....online superpage construction could be extended to provide additional benefits, such as improving I O performance. 55 3.8. 1 Alternative TLB Hardware Since the original measurements for this chapter were made, TLB sizes have been increasing in response to growing application memory requirements [Dig 97] Some systems include set associative TLBs, allowing larger TLBs to be built with the same access time as a smaller fully associative TLB [Uhlig et al. 94] Others have proposed building a software cache of the TLB to reduce TLB miss times [Bala et al. 94] The impact of superpage construction ....

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Digital Equipment Corporation. Digital Semiconductor 21164 Alpha Microprocessor Hardware Reference Manual, February 1997.

....[1] SimOS Alpha is a full system simulation environment that simulates the hardware components of Alpha based multiprocessors (processors, MMU, caches, disks, console) in enough detail to run Alpha system software. Specifically, SimOS Alpha models the micro architecture of an Alpha processor [4] and runs essentially unmodified versions of Digital Unix 4.0 and PALcode. The ability to simulate both user and system code under SimOS Alpha is essential given the rich level of system interactions exhibited by commercial workloads. For the OLTP runs in this study, the kernel component is ....

Digital Equipment Corporation. Digital Semiconductor 21164 Alpha microprocessor hardware reference manual, March 1996.

....study MIPS based multiprocessors. Our version of SimOS simulates the hardware components of Alpha based multiprocessors (processors, MMU, caches, disks, console) in enough detail to run Digital s system software. Specifically, SimOS Alpha models the micro architecture of the Alpha 21164 processor [5] and runs essentially unmodified versions of Digital Unix 4.0 and the 21164 PALcode. SimOS Alpha supports multiple levels of simulation detail, enabling the user to choose the most appropriate trade off between simulation detail and slowdown. Its fastest simulator uses an on the fly binary ....

Digital Equipment Corporation. Digital Semiconductor 21164 Alpha microprocessor hardware reference manual, March 1996.

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