D. Doukas and A. S. LaPaugh. Clover: A timing constraints verification system. Specification and Synthesis of Digitial Systems, 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....where our algorithm fails to compute exact results. Section 2.6 presents results of applying our algorithm to a suite of asynchronous benchmarks. Finally, Section 2. 7 summarizes the contributions of this chapten A large number of min max timing simulators are described in the literature [12, 73, 10, 52, 51, 33, 88, 65, 64, 31]. However, most of these are not well suited for our purpose because of of the following reasons: 1. They require the user to specify the relative input transition times, which is usually not known in advance in asynchronous circuits, or 2. They have worst case exponential complexity, which ....

D. Doukas and A. S. LaPaugh. Clover: A timing constraints verification system. Specification and Synthesis of Digitial Systems, 1990.

....algorithm fails to compute exact results. Section 2.6 presents results of applying our algorithm to a suite of asynchronous benchmarks. Finally, Section 2.7 summarizes the contributions of this chapter. 2. 2 Related Work A large number of min max timing simulators are described in the literature [12, 73, 10, 52, 51, 33, 88, 65, 64, 31]. However, most of these are not well suited for our purpose because of of the following reasons: 1. They require the user to specify the relative input transition times, which is usually not known in advance in asynchronous circuits, or 2. They have worst case exponential complexity, which ....

D. Doukas and A. S. LaPaugh. Clover: A timing constraints verification system. In Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digitial Systems, 1990.

....both its power and complexity. Attempts to reason about digital systems have been ongoing [1 3] Various methods for modeling the systems with time delay have been proposed and formal verification methods investigated[4 7] Methods based on simulation have also been used to verify circuits[8,9]. Other recent work has taken a symbolic approach to attempt to reason about circuits[10,11] and our earlier work[12, 13] investigated a more simplistic verification technique upon which this work is based. Recent work in asynchronous verification [14] performs an analysis similar to our search ....

Dimitrie Doukas & Andrea S. LaPaugh, "CLOVER: A Timing Constraints Verification System," Proceedings of the 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU '90), New York, NY, SIGDA (Aug., 1990).

.... The Verification Problem Attempts to reason about digital systems have been ongoing for many years [1 3] Various methods for modeling time delays have been proposed and formal verification methods investigated [4 7] Methods based on simulation have also been used to verify circuits[8,9]. Recent work has taken a symbolic approach to attempt to reason about circuits [10,11] as well as our previous work [12,13] which investigated a simpler verification technique, upon which this work is based. As in our previous work, our goal is to provide a technique for automatically verifying ....

Dimitrie Doukas & Andrea S. LaPaugh, "CLOVER: A Timing Constraints Verification System," Proceedings of the 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU '90), New York, NY, SIGDA (Aug., 1990).

....[13] The complexity of the problem can be attributed to two primary causes. First, exponentially long sequences of transitions can result from a single input change in certain circuits [8] Many event driven simulators suffer from exponential worst case behavior because of this problem [21, 2, 15, 10, 20, 19, 9]. Second, the number of different possible gate delay combinations can be exponential in the circuit size. Since the circuit output depends on the choice of gate delays in general, determining the exact minimum and maximum gate switching times involves ex This work was supported by a grant from ....

....of certain types of circuits, e.g. 3D circuits with conditional inputs [23] However, there does not exist any logic value in Kung s algebra to model such waveforms. We then present a polynomial time algorithm for minmax timing simulation of combinational circuits. Unlike other simulators [21, 10, 19], our simulation algorithm does not assume prior knowledge of when the primary inputs transition relative to each other, and computes bounds on the signal propagation delays from each primary input to each gate in the circuit. In order to improve the accuracy of simulation, we also present a ....

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D. Doukas and A. S. LaPaugh. Clover: A timing constraints verification system. ACM International Workshopon Timing Issues in the Specification and Synthesis of Digitial Systems, 1990.

.... somewhat related because they are also concerned with timing issues although they usually consider lower levels of abstraction: Avrunin et al. 5] Jahanian and Mok [68] Coolahan and Roussopoulos [66] Jahanian [67] Khordoc et al. 81] Liu and Ha [91] Martello et al. 93] Doukas and LaPaugh [36], and Wallace and Sequin [117] 4.4 Summary In this chapter, we have discussed the derivation and validation problems in general. x 4.1 has defined these problems with an overview of our solution, and x 4.2 has examined the issue of using average values rather than the worst case ones in our ....

D. Doukas and A. S. LaPaugh. CLOVER: A timing constraints verification system. In Proc. 28th Design Automation Conf., pages 662--7. ACM/IEEE, June 1991.

....Most incomplete verifiers (e.g. SCALD [McWilliams 80] and TDS [Kara et al. 88] provide little support for specifying and verifying temporal properties other than simple setup and hold constraints. One incomplete verifier that supports a more expressive specification language is CLOVER [Doukas LaPaugh 91] which uses an event based specification language (ATCSL) that relies on event indexing to identify the discrete events being constrained. OEsim could be classified as a verifier because it compares two different specifications: the operational specification described by the operation event ....

D. Doukas and A. S. LaPaugh. CLOVER: a timing constraints verification system. In 28th ACM/IEEE Design Automation Conference, June 1991. 141

....at least 10ns before the falling transition of AS L can occur. This is reflected by the associated timing annotation in the protocol signal transition graph. These timing constraints must be verified after the synthesis process, using for example the timing verification techniques reported in [2, 14, 19, 8]. protocol rtzRead; protocol rtzWrite; process shift send : in signal start; channel addrh7:0i, datah7:0i: rtzRead; channel addr outh7:0i, data outh7:0i: rtzWrite; f boolean xh7:0i, yh7:0i; start ; addr y k data x; addr out y k data out (xAE2) start Gamma; g Figure 5: A simple shift send ....

D. Doukas and A. S. LaPaugh. Clover : A timing constraints verification system. In 28th ACM/IEEE Design Automation Conference, June 1991.

....operation. A timing analysis tool for 3D circuits is also described. Section VI presents results of applying our timing analysis tool to a suite of 3D benchmarks. Finally, we conclude the paper in Section VII. II. RELATED WORK A large number of min max timing simulators [18] 20] 21] 17] [22], 19] 23] 24] 25] are described in the literature. However, most of these are not suitable for our purpose because: a) they require the user to specify the relative transition times of the primary inputs, which is contrary to our requirements: we would like to determine constraints on ....

D. Doukas and A. S. LaPaugh, "Clover: A timing constraints verification system," in Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digitial Systems, 1990.

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