Robert J. Greiner. 88110 Message Coprocessor User's Manual. Motorola Computer Group, February 1992. DRAFT. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Hardware Mechanisms for Efficient Interprocessor Communication - Henry (1996) (Correct)
....and accessed by the register field of any instruction. They could also sit in separate storage and be accessed via new opcodes or reserved coprocessor opcodes. Finally they could be mapped to certain memory locations in the processor cache or main memory. For example, the 88110MP microprocessor [Gre92, Bec92] contains an on chip network interface with dispatch hardware optimizations similar to those described in this chapter. The 88110MP network interface sits on the processor s source and write back buses along with all the other functional units. The 88110MP is dual issue and the network ....
Robert J. Greiner. 88110 Message Coprocessor User's Manual. Motorola Computer Group, February 1992. DRAFT.
A Tightly-Coupled Processor-Network Interface - Henry, Joerg (1992) (61 citations) (Correct)
....and accessed by the register field of any instruction. They could also sit in separate storage and be accessed via new opcodes or reserved coprocessor opcodes. Finally they could be mapped to certain memory locations in the processor cache or main memory. For example, the 88110MP microprocessor [Gre92] Bec92] contains an on chip network interface with dispatch hardware optimizations similar to those described in this paper. The 88110MP network interface sits on the processor s cache bus processor chip net reg net interface 2nd level cache 2nd level cache Figure 8: An off chip cache based ....
Robert J. Greiner. 88110 Message Coprocessor User's Manual. Motorola Computer Group, February 1992. DRAFT.
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