Meerbergen, J., Lippens, P., Verhaegh, W., and Werf, A. V. D. "PHIDEO: High Level Synthesis for High Throughput Applications". Journal of VLSI Signal Processing (May 1995). http://www.research.philips.com/pressmedia/releases/e14.html.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....guides high level synthesis algorithms to architectures exhibiting these characteristics. There are synthesis approaches that focus on array and multi dimensional loop based designs like the motion estimation example above, and the designs they generate tend to have the characteristics above [2, 3]. There have also been studies in background memory synthesis for similar application classes [4, 5, 6] However, all these approaches require that the behavior be described in loops and arrays, and that array indices to the arrays be linear expressions. Our model allows us to synthesize designs ....

....transfer subsystem without considering their interdependence [9, 10, 11] This could prematurely prune the search space for storage and data transfer subsystem synthesis. More recent HLS systems do consider the effects of operation scheduling and binding on the storage and data transfer subsystem [12, 3, 13]. Most use an estimate of the minimum numbers of registers, ports, and buses needed 4 in any clock cycle. They make no explicit efforts to broadcast data being used multiple times and have no explicit mechanisms ensuring data is used soon after it is produced. They rely on minimizing the ....

J. L. V. Meerbergen, P. E. R. Lippens, W. F. J. Verhaegh, and A. Van Der Werf, "Phideo: High Level Synthesis for High Throughput Applications," Journal of VLSI Signal Processing, vol. 9, pp. 89--104, May 1995.

....step after the execution unit has been synthesized. Some systems completely decouple execution unit synthesis from synthesis of the storage and data transfer subsystem [1, 2, 3] Others use simple models for these subsystems to account for effects on them during the synthesis of the execution unit [4, 5, 6]. Some HLS tools are specialized to generate extremely efficient architectures for algorithms that can be described as arrays and multidimensional loops [7, 5] However, they are limited to applications described in that manner. Researchers in the past have stressed the importance of ....

.... [1, 2, 3] Others use simple models for these subsystems to account for effects on them during the synthesis of the execution unit [4, 5, 6] Some HLS tools are specialized to generate extremely efficient architectures for algorithms that can be described as arrays and multidimensional loops [7, 5]. However, they are limited to applications described in that manner. Researchers in the past have stressed the importance of data transfers in HLS [8, 9] The DTmodel is a new method for formulating HLS using data transfers as the basic entity in synthesis as opposed to the tradition model that ....

J. L. V. Meerbergen, P. E. R. Lippens, W. F. J. Verhaegh, and A. Van Der Werf, "Phideo: High Level Synthesis for High Throughput Applications," Journal of VLSI Signal Processing, vol. 9, pp. 89--104, May 1995.

....inputs and outputs are obtained from RT simulations [2] or from the data flow graph [4] Although macro modeling seems very promising, it is limited its applications. It targets specific applications based on fixed building blocks and cannot cope with flexible architectural synthesis tools [5] or handwritten VHDL code. Furthermore, each change in technology, synthesis or layout tool, or in the structure of the building blocks requires a considerable recharacterization of the power models. A different approach in high level power estimation is currently being developed [3, 6] This ....

....24 multiplications and 24 additions. Several variants have been made of this architecture, by reducing the number of resources (multipliers and adders) and hence introducing time multiplexing. Variants with 1, 2, 3, 4, 6, 8, 12, and 24 multipliers and adders have been generated by Phideo [5], an in house architectural synthesis tool. The size of the largest variant (24 resources) was 1.7 mm2 in a 0.5u technology. Figure 4 shows the energy dissipation for 200 random input samples for the different variants of this filter. Figure 4: Results of design space exploration for FIR filter. ....

J.L. v. Meerbergen et al., "PHIDEO: High-Level Synthesis for High Throughput Applications", J. of VLSI Signal Processing, 9, 95, pp. 89-104.

....in to the timing analysis. We illustrate these ideas using the dashboard controller [1] as an example. 1. 3 Related Earlier Work There has been a lot of excellent earlier work on modeling communications systems [6, 21, 23, 11] There are several tools, like MISTREL [22] PTOLEMY [19] PHIDEO [24], PROPHID [15, 16] that include communication specification and sharing of channels among various tasks. However, most of these tools do not address the problem at the level of abstraction that we do in this paper. Also, some of these tools, like PROPHID and PHIDEO are specific to the digital ....

J.L. Van Meerbergen, P.E.R. Lippens, W.E.J. Verhaegh, and A. Van der Werf. Phideo: high-level synthesis for high throughput applications. Journal of VLSI Signal Processing, 9(1-2):84--104, Jan 1995.

....Hence digital signals are usually of the fixed point type as this leads to hardware and power savings for the required computational performance. The periodic sampling makes a digital signal appear as a regular stream of digital words which are naturally structured into multi dimensional arrays [40]. An obvious example is image processing where every grey scale image frame is a two dimensional array in space with a repetition or frame period T f (sec) 2.1.2. DSP Systems In the strictest sense DSP systems are algorithms mapping digital signals into digital signals in real time. The ....

....31, 36] and will be reported in the chapter by Goossens. Hardware accelerator in Table 1 refers to the lowly multiplexed data paths. As discussed above, they are needed to meet the high data rate requirements in DSP. Several accelerator compilers have been reported such as CATHEDRAL 3 [29] PHIDEO [40], and HYPER [33] User interface and control parts of the specification can also be mapped on a micro controller if there is a strong need for future product redefinition. Otherwise synthesis of co operating hardware FSMs may be cheaper in area and power requirements. In the latter case, existing ....

J. van Meerbergen et al. PHIDEO: High-level synthesis of high throughput applications. Journal of VLSI Signal Processing, 9(1-2):89 -- 104, January 1995.

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Meerbergen, J., Lippens, P., Verhaegh, W., and Werf, A. V. D. "PHIDEO: High Level Synthesis for High Throughput Applications". Journal of VLSI Signal Processing (May 1995). http://www.research.philips.com/pressmedia/releases/e14.html.

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