GRANT,D.M.,MEERBERGEN,J.V.,AND LIPPENS, P. E. R. 1994. Optimization of address generator hardware. In Proceedings of the 1994 Conference on European Design and Test (Paris, France, Feb.). 325--329. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Performance-Area Trade-Off of Address Generators for.. - Hettiaratchi, Cheung, .. (2002) (Correct)
....[6] The address allocation task of PHIDEO trades off memory size against addressing cost. ZIPPO tool which is integrated with PHIDEO considers several address streams accessing different memory modules on chip, and synthesises an address generator that is area optimized by sharing hardware [5]. The combined ADOPT methodology for address generator synthesis described in [8] is a general framework for optimizing address generators. ADOPT considers both counter based and arithmetic based address generator styles and also considers hardware sharing. Schmit and Thomas employ some ....
D. Grant, J. V. Meerbergen, and P. Lippens. Optimization of address generator hardware. In Proceedings of the European Design and Test Conference, pages 325 -- 329, Feb. 1994.
Address Equation Multiplexing For Real-Time Signal.. - Miranda, Catthoor, De.. (1994) (Correct)
....work is that every address equation is mapped to a separate hardware unit which can result in significant area inefficiency, especially for complex distributed memory organizations as in video and image processing. Recently, some support for multiplexing has been introduced in the ZIPPO toolbox [7] which is mainly oriented to bit level address merging. However, the sharing related decisions are heavily manually steered there, especially amongst different address words. The back end of our hardware address generation toolbox is derived from this work at Edinburgh and Philips [4, 5] where we ....
D.Grant, J. van Meerbergen, and P.Lippens. Optimization of address generator hardware. In Proc. 5th ACM/IEEE Europ. Design and Test Conf., pages 325-- 329, Paris, France, Feb. 1994.
High-level Address Optimisation and Synthesis Techniques .. - Catthoor, Janssen, De.. (1998) (3 citations) (Correct)
....cost in the ACUs and not on the program ROM and associated decoders. Most of the work found in literature for custom addressing focusses on bit level optimisations for architectures combining counters and look up tables [8] 7] with some interactive support for multiplexing HW at that level [9]. However, time sharing at the address sequence level which we have shown [10] to be crucial to reduce the overall cost is almost not considered there. On the other hand, architecture exploration support for target styles different from counter based architectures, only have been addressed ....
....realized as a counter modified by a two or multilevel logic filter. This style requires an explicit expansion of the AEs, so it can be applied only to manifest (compiletime known) accesses. It was first introduced by the Univ. of Edinburgh [18] 8] and used in different compiler contexts [7] [9], 19] where further bit level optimisations have been proposed. Counter based architectures require two control lines to obtain the next memory address, and to set the addressing unit to an initial state. These lines can be generated from the global master cMMU controller. In the cACU case, the ....
D.Grant, J.Van Meerbergen, P.Lippens, Optimization of address generator hardware, Proc. 5th ACM/IEEE European Design $ Test Conf., pp. 325-329, 1994.
Dataflow-driven Memory Allocation for Multi-dimensional Signal.. - Balasa, al. (1994) (10 citations) (Correct)
....HLMM domain within a high level or system level synthesis context. Most effort up to now has concentrated on detailed in place storage of M D signals to reduce the memory size [27, 28, 14, 21] and on address cost reduction by optimising the address sequences and the address generation circuitry [11]. However, on top of this it is possible to identify several other crucial synthesis tasks. In particular, we have addressed global control flow optimisations intended to reduce the total memory cost [29, 8] The latter can lead to active area savings of several orders of magnitude when compared ....
D.Grant, J.van Meerbergen, P.Lippens, "Optimization of address generator hardware", Proc. 5th ACM/IEEE Europ. Design and Test Conf., Paris, France, pp.325--329, Feb. 1994.
Co-Design Of DSP Systems - De Man, Bolsens, Lin, Van Rompaey.. (1996) (5 citations) (Correct)
....internally over shared memory. Interprocess communication is over unidirectional channels using an RPC protocol. 2. Box 3 in Figure 3 contains four consecutive steps. First, for array intensive DSP code optimisation takes place to optimise memory and power dissipation in memory accesses [1, 6, 15, 25, 26, 42]. This is followed by an interactive coarse partitioning of the specifications over a user allocated architecture. This leads to a merger of a number of compiler consistent processes to be mapped on the same component. The implication is that hardware and software (run time kernels, software ....
D. M. Grant et al. Optimization of address generator hardware. In Proceedings of the European Design and Test Conference, ED&TC 1994, pages 325 -- 329. Paris, France, February 1994.
Data and Memory Optimization Techniques for Embedded.. - Panda, Catthoor, Dutt, .. (2001) (14 citations) (Correct)
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GRANT,D.M.,MEERBERGEN,J.V.,AND LIPPENS, P. E. R. 1994. Optimization of address generator hardware. In Proceedings of the 1994 Conference on European Design and Test (Paris, France, Feb.). 325--329.
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