E.E. Johnson. Graffiti on the memory wall. Computer Architecture News, 23(4):7--8, September 1995. Home/Search Document Not in Database Summary Related Articles Check |
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Computer Architecture: a qualitative overview of Hennessy and.. - Machanick (2001) (Correct)
....Dulong [1998] discusses some features of the Intel IA 64 architecture, and some performance results for limited aspects of the architecture have been published [August et al. 1998] VLIW is briefly discussed in Section 4.4 of the book, starting on page 278. Some researchers [Wulf and McKee 1995, Johnson 1995] have claimed that we are approaching a memory wall, in which all further CPU speed improvements will be limited by DRAM speed. RAMpage is a new strategy for memory hierarchy, in which the lowest level of cache becomes the main memory and DRAM becomes a paging device, to improve effectiveness of ....
EE Johnson. Graffiti on the Memory Wall, Computer Architecture News, vol. 23, no. 4, September 1995, pp 7-8.
Performance Implications of Context Switches on Misses to DRAM - Meerdervoort (1999) (Correct)
....masking the lower performance of main memory. However, the effectiveness of caches is ultimately limited as the CPU DRAM speed gap widens further, with threats of a looming memory wall a barrier to further performance improvement imposed by the memory system [Wulf and McKee 1995, Wilkes 1995, Johnson 1995] 1.2 Proposed Solution As lagging DRAM speed continues to degrade system performance, methods used by operating systems in dealing with slow disk drive devices start to look attractive. The delay caused by a disk access may run into millions of CPU cycles, prompting the use of context ....
E Johnson. Graffiti on the Memory Wall, Computer Architecture News, vol. 23 no. 4, September 1995, pp 7-8.
An SRAM Main Memory Model - Salverda (1997) (1 citation) (Correct)
....may thus be prevented from improving CPU cycle time because the primary cache, being resident on chip, forms part of the processor s critical timing path. That these trends do indeed represent a matter of concern for hardware designers is reflected in a number of predictions of a memory wall [20, 45, 46], a point in the near future at which system performance will be determined entirely by the speed of DRAM; any improvements in processor speed will no longer have an effect on application execution time. While such predictions may well turn out to be overly pessimistic, they nonetheless ....
....fetch in itself constitutes a memory reference. Hence, the argument presented here considers only memory references generated by load and store instructions. A similar discussion, but one which employs a more realistic value for the number of memory references per instruction, appears in Johnson [20]. Parameter Primary cache Secondary cache Block size 4B 32B 32B 256B Hit time 1 2 cycles 6 15 cycles Miss penalty 8 66 cycles 30 200 cycles Miss rate 1 20 15 30 Capacity 1KB 128KB 256 KB 16MB Table 3.1 : Typical parameters for the primary and secondary caches ....
E.E. Johnson. Graffiti on the memory wall. Computer Architecture News, 23(4):7--8, September 1995.
Preliminary Investigation of the RAMpage Memory Hierarchy - Machanick, Salverda (1998) (Correct)
....hierarchy (as simulated) in that performance degrades less as DRAM reference costs increase. keywords: memory hierarchy, caches, paging, software controlled replacement CR categories: B.3, C.4, D.4. 2 1 Introduction There has been much discussion in recent years of the memory wall [WM95, Joh95, Wil95] a consequence of a growing CPU DRAM speed gap [HJ91, BD94] One approach to dealing with this growing CPU DRAM speed gap is to focus on strategies for reducing misses, even if those strategies make each miss cost more. For example, work on softwarecontrolled caches in the past [CSB86] ....
E.E. Johnson. Graffiti on the memory wall. Computer Architecture News, 23(4):7--8, September 1995.
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy - Machanick, Patel Self-citation (Memory) (Correct)
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E.E. Johnson. Gra#ti on the memory wall. Computer Architecture News, 23(4):7-- 8, September 1995.
Scalability of the RAMpage Memory Hierarchy - Philip Machanick Department (2000) (Correct)
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E.E. Johnson. Graffiti on the memory wall. Computer Architecture News, 23(4):7--8, September 1995.
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