H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, R. K. Iyer, "A fast and accurate gate-level transient fault simulation environment". Proceedings 23rd Symp. on Fault-Tolerant Computing Systems (FTCS-23), Toulouse (France), pp. 310-319, June, 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....(the processor cycle is 1000 ns. In some experiments, the duration is randomly generated in the range [0.1T10. 0T] where T is the CPU clock cycle. It is been intended to inject short faults, with a duration equal to a fraction of the clock cycle (the most common faults, as described in [30]) as well as long faults, which will ensure in excess the propagation of the errors to the detection signals. 9. Analysis results: For every injection experiment, two files are compared: the simulation result with and without fault. The estimated coverages and latencies of the detection and ....

H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, R. K. Iyer, "A fast and accurate gate-level transient fault simulation environment". Proceedings 23rd Symp. on Fault-Tolerant Computing Systems (FTCS-23), Toulouse (France), pp. 310-319, June, 1993.

....T 1 d comp perform several hundreds of thousand of simulations at it was done in the evaluation. Thus, we have used the Verilog XL logic simulator that offers also the necessary timing accuracy. A more dedicated simulator for transient faults could also be used for these experiments [CHA 93] Transient pulses of duration up to 1ns have been used to validate the principle. This duration is much higher than the practical transient pulses induced by particle strikes. As concerning injection of timing faults, we added delays within the circuit paths. Delays up to 20 of the maximum ....

H. CHA et al, "A Fast and Accurate Gate-level Transient Fault Simulation Environment", Proceedings of FTCS, June 1993

....II. The fault remained in the register until the next time the register was updated by the processor. The single bit flip model is used because it is a reasonably accurate fault model for transient faults, despite its simplicity. Gate level fault simulations of sequential 2 benchmark circuits [1] and device level simulations of the 68000 in which small charges were injected [2] showed that 90 manifest as single bit flips in internal registers. Furthermore, physical heavy ion fault injection experiments on the 68000 and 68070 using a 232 Californium source showed that 90 to 95 of all ....

H. Cha, E. Rudnick, G. Choi, J. Patel, R. Iyer, "A Fast and Accurate Gate-Level Transient Fault Simulation Environment, " in Proc. IEEE Annual 23rd Int. Symp. on Fault-Tolerant Computing, FTCS-23, June 1993, pp. 310-319.

....fault manifestations, it can not be used to determine reliability parameters like mean time to failure. Choi et al. 4] injected transient faults in a model of a jet engine controller by using the mixed mode simulator SPLICE. Another mixed mode fault simulation approach has been presented by Cha [6], where transient gate level faults have been injected by using a combination of a timing fault simulator (TIFAS) and zero delay parallel fault simulator TPROOVES to speed up the simulation time. REACT [7] DEPEND [10] and SIMPAR [14] are tools which allow building up and evaluating models of ....

H. Cha, E. Rudnick, G. Choi, J. Patel, R. Iyer "A Fast and Accurate GateLevel Transient Fault Simulation Environment", Proc. 23rd Symp. on Fault-Tolerant Computing (FTCS-23), Toulouse, France, June 1993, pp. 310-319.

....the fault tolerance through time redundancy. Therefore, performance penalty is unavoidable, and the only remaining question is how to minimize the performance impact and still achieve the desired level of fault tolerance. Using an updated version of the transient fault simulator described in [5], we inject transient pulses into ISCAS 89 benchmark circuits to study the effectiveness of the latch designs for tolerating transient pulses. Although we are looking at transient pulses caused by alpha particles, the latches can tolerate transient pulses in general, no matter what the root cause ....

....as the transistor strength, the total charge collected, and the total capacitance at the node [7] The transient pulse thus produced will travel down the circuit, and it may be latched depending on its arrival time with respect to the clock edge of the flipflops. A flip flop has latching windows [5] in the neighborhood of the clock edge in which the transient pulse will be latched, as shown in Figure 1. The Earliest Time and the Latest Time define the limits of the latching window. Latching windows vary for different flip flop designs and for different pulse widths. Typically, the latching ....

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H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, and R. K. Iyer, "A fast and accurate gate-level transient fault simulation environment," Digest, 23th Int. Symp. Fault-Tolerant Comput., June 1993, pp. 310319.

....simulators such as SPICE3 [1] are too slow on even a moderate sized circuit. Mixedmode simulators have been developed and used to speed up the simulation time, but even these are not fast enough [2, 3] Recently, gate level simulators have been employed to drastically improve the simulation time [4, 5]. However, gate level simulators are only This research was supported by Joint Electronic Service Program Contract N00014 J 90 1270. as good as the model which maps the electrical level particle effect into logic level effect. The goal of this research is to develop a computationally efficient ....

....to equivalent inverters. At the time of the fault injection, the affected inverter may be switching, or it may be at a stable high or low. Since recent work indicates that transient faults injected before the circuit has settled for the clock cycle rarely manifest themselves as latched errors [5], we will not consider the case of transitioning inverter at the time of fault injection. Furthermore, of the two possible remaining cases as shown in Figure 2, we will only consider (a) since the case shown in (b) can be analyzed in a similar manner. 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 25 30 35 40 ....

H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, and R. K. Iyer, "A fast and accurate gate-level transient fault simulation environment," to appear in Digest, 23rd Int. Symp. Fault-Tolerant Comput., June 1993.

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H. CHA, E. RUDNICK, G. CHOI, J. PATEL, R. IYER, "A fast and accurate gate-level transient fault simulation environnement", Digest, 23th Int. Symp. Fault-Tolerant Computing, June 1993, pp. 310319.

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