| A. Hekmatpour, et al. "Hierarchical Modeling of the VLSI Design Process", IEEE Expert, pp. 56 - 70, April 91. |
....on providing either efficient knowledge based systems for a specific application domain at a low level of abstraction, or design management assistance for a particular VLSI task. For example, SISC [15] is a frame based system, customised to represent knowledge about integrated circuits. Kinden [14] is an experimental knowledge based intelligent environment for the VLSI design process. Micon1 [11] is a synthesis tool that aims to automate the design of computer systems. DEBYS (Design BY Specification) 12] covers both operative and technological specifications for digital and analog systems. ....
A. Hekmatpour, et al. "Hierarchical Modeling of the VLSI Design Process", IEEE Expert, pp. 56 - 70, April 91.
....on providing either efficient knowledge based systems for a specific application domain at a low level of abstraction, or design management assistance for a particular VLSI task. For example, SISC [15] is a frame based system customized to represent knowledge about integrated circuits. Kinden [14] is an experimental knowledge based intelligent environment for the VLSI design process. Micon1 [12] is a synthesis tool that aim to automate the design of computer systems. Our research differs from these efforts by proposing an intelligent and flexible architecture able to manage the reusability ....
A. Hekmatpour, et al. "Hierarchical Modeling of the VLSI Design Process", IEEE Expert, pp. 56 - 70, April 91.
....for the KBS acceptance, system intelligence has to be accessible to end users. Such system should provide convinient updating and knowledge base modification. Hierarchical Knowledge bases Our knowledge base architecture is an extension of the Bourne et al. proposal and our previous work [Hekmat91] whereby, the expert s knowledge about the behavior of the environment is represented as a Behavioral Hierarchy Knowledge Base (BHKB) Next, a number of knowledge bases representing the expert s knowledge about the physical and structural hierarchy of the environment, called Structural Hierarchy ....
A. Hekmatpour, A. Orailoglu, and Paul Chau, "Hierarchical Modeling of the VLSI Design Process," IEEE EXPERT, 6(2):56--70, April 1991. Submitted to the International Expert System Journal of Research & Development Amir Hekmatpour, IBM MTC, rima@vnet.ibm.com -- 12 --
....level knowledge modules concern individual VLSI design tools, while knowledge at the lowest level consists of UPERIT templates. What the top level module specifically contains is knowledge about how different tools and stages of the VLSI design process are related to each other. We follow [10] in partitioning the design process into algorithm, architectural, structural, functional, logical, transistor, technology, physical, package, and fabrication stages. This module includes, for example, the knowledge that ETE is involved in the tasks of functional and logical design. The top and ....
Amir Hekmatpour, Alex Orailoglu, and Paul Chau. Hierarchical modeling of the VLSI design process. IEEE Expert, 6(2):56--70, April 1991.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC