Mikschl, A. & Damm, W. [1996], MSPARC: A multithreaded sparc, in L. Bouge, P. Fraigniaud, A. Mignotte & Y. Robert, eds, `EuroPar '96 Parallel Processing: Second International Euro-Par Conference, Vol. II', LNCS 1124, Springer Verlag, pp. 461--469.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....has rarely been explored in context of microcontrollers for handling of external hardware events. Besides our own approach, the EVENTS mechanism [8] proposes a FPGAbased processor external hardware scheduler that triggers context switches in a single or in multiple multithreaded MSparc processors [9]. This paper investigates real time scheduling algorithms suitable for multithreaded processors and presents performance evaluations on our evaluation testbed a multithreaded Java microcontroller called Komodo. Section 2 shortly describes the proposed Komodo microcontroller. Section 3 focuses ....

W. Damm, A. Mikschl. MSPARC: a multithreaded SPARC. Euro-Par'96 Parallel Processings: Second International Euro-Par Conference, Vol II, LNCS 1124, Springer Verlag 1996.

....has rarely been explored in context of microcontrollers for handling of external hardware events. Besides our own approach, the EVENTS mechanism [8] proposes a FPGAbased processor external hardware scheduler that triggers context switches in a single or in multiple multithreaded MSparc processors [9]. This paper investigates real time scheduling algorithms suitable for multithreaded processors and presents performance evaluations on our evaluation testbed a multithreaded Java microcontroller called Komodo. 2 The proposed Komodo microcontroller The Komodo microcontroller [10] is a ....

W. Damm, A. Mikschl. MSPARC: a multithreaded SPARC. Euro-Par'96 Parallel Processings: Second International Euro-Par Conference, Vol II, LNCS 1124, Springer Verlag 1996.

....systems or controllers for fast running manufacturing cells. One part of our system is a universal prototype hardware architecture that consists of an FPGA field and several processor nodes. Each node is equipped with a multi threaded implementation of the SPARC processor, called MSPARC [15], which is optimized for embedded control applications. This paper concentrates on the second part of the system, a HW SW cosynthesis environment, where we use two graphical formalisms, real time symbolic timing diagrams [5] and statecharts [9] to specify ECAs and combine them with tools for ....

A. Mikschl and W. Damm. MSPARC: A multithreaded Sparc. In L. Bouge, P. Fraigniaud, A. Mignotte, and Y. Robert, editors, Euro-Par'96 Parallel Processing: Second Int. Euro-Par Conf., Vol. II, LNCS 1124, pages 461--469. Springer Verlag, 1996.

....that enables users to generate, synthesize and download code for this board automatically starting from graphical specifications with real time constraints. To meet the first of these goals we propose a hardware architecture that consists of FPGAs and multithreaded processors called MSparc [Mikschl Damm 1996]. This architecture can be integrated with the physical system that is to be controlled by the application (universal prototype) The MSparc processors allow for the processing of sensor input to start only a few cycles after the input has been signaled. The second goal is met by using two ....

....the multithreaded processors (see sections 2.2 and 3.2) Node Node Node Node RAM Dual Ported Timer Interface FPGAField Set Interrupt Processor Ctrl, Ready Memory Access Memory Access Figure 1: The HW architecture 2. 2 Processor The processor we use in the nodes of our architecture is the MSparc [Mikschl Damm 1996]. This processor is compatible to a standard Sparc processor [Sparc International Inc. 1992] and, additionally, supports multithreading for up to four contexts on chip. The MSparc has a five stage pipeline and a 8 KB on chip instruction cache. The cache is statically divided in four parts, one ....

Mikschl, A. & Damm, W. [1996], MSPARC: A multithreaded sparc, in L. Bouge, P. Fraigniaud, A. Mignotte & Y. Robert, eds, `Euro-Par'96 Parallel Processing: Second International Euro-Par Conference, Vol. II', LNCS 1124, Springer Verlag.

....LimitLESS directories. Latencies still occur although communication locality is enhanced by runtime and compile time partitioning and placement of data and processes. MSparc: An approach similar to the Sparcle processor is taken at the University of Oldenburg (Germany) with the MSparc processor [156,179]. MSparc supports up to four contexts on chip and is compatible to standard Sparc processors. Switching is supported by hardware and can be achieved within one processor cycle. The multithreading policy is block interleaving with the switch on cache miss policy as in the Sparcle processor. ....

A. Mikschl and W. Damm, Msparc: A multithreaded Sparc, Lect. Notes Comp. Sc., 1123, Springer-Verlag, Berlin, 1996, pp. 461469.

No context found.

Mikschl, A. & Damm, W. [1996], MSPARC: A multithreaded sparc, in L. Bouge, P. Fraigniaud, A. Mignotte & Y. Robert, eds, `EuroPar '96 Parallel Processing: Second International Euro-Par Conference, Vol. II', LNCS 1124, Springer Verlag, pp. 461--469.

....locks the specified address if it was not already locked. If it was, then the instruction is only completed iff address becomes unlocked. ffl UNLOCK address The specified address becomes unlocked. It is implementation dependent 2 These instructions are also briefly covered in [Risau, Mikschl Damm 1996] whether unlocking an address that was not locked produces an error or is tolerated. ffl COPY BACK node, address, nr of addresses This instruction affects all cache lines in the cache of processor node containing data with addresses between (and including) address and address nr of ....

....even if the new value is only in the buffer and not yet actually written to memory. Messages in out queue are to be send to the bus. This queue is an optimization since for the processor and the memory controller sending of a message ends when the 3 The MSparc processor is being discussed in [Mikschl Damm 1996]. 6 6 6 oe6 6 oe 6 oe oe . 6 memory cache cache controller in queue out queue memory queue Network Interface Unit memory controller MSparc processor physical address space virtual address space bus control bus out bus in ....

Mikschl, A. & Damm,W. [1996], MSPARC: A multithreaded sparc, in L. Bouge, P. Fraigniaud, A. Mignotte & Y. Robert, eds, `Euro-Par'96 Parallel Processing: Second International Euro-Par Conference, Vol. II', LNCS 1124, Springer Verlag.

....error 3 that would occur in sequentially consistent systems, too. 3 Implementation The primitives presented in the last section have been implemented in a VHDL model of the WAMCOT Architecture. WAMCOT is a shared memory NUMA architecture, with an optical bus ( AG92] multithreaded processors ([AD96]) and a weak cache coherence protocol based on these primitives. The VHDL model showed the feasibility of the protocol but did not lend itself very well to a simulation with real benchmarks. Toy benchmarks yielded a processor utilization of up to 83 , which encourages us to further pursue our ....

A.Mikschl and W. Damm. MSPARC: A multithreaded Sparc. In EuroPar 96. Springer LNCS (this volume), 1996.

No context found.

A. Mikschl, W. Damm, MSparc: A multithreaded sparc, in: Euro-Par, Vol. II, 1996, pp. 461-469.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC