N. Topham, A. Gonz alez, and J. Gonz alez. The Design and Performance of a Conflict-Avoiding Cache. In Proc. of the 30th Annual International Symposium on Microarchitecture (MICRO-30), pages 71--80, Research Triangle Park, NC, Nov. 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....choice, although they perform relatively well. Irreducible polynomials offer no measurable benefits over reducible polynomials, while they may be a lot more complex to implement. 1 Introduction Randomising set index functions can remove a significant amount of conflict misses in data caches [11, 15] by spreading the cache blocks uniformly over all sets. Instead of selecting a slice of bits from the block address to index a cache, a randomising set index function computes a more complex function of the address, e.g. using exclusive or s (XOR) We will use the shorter term randomisation ....

....function when we mean randomising set index function. Although some work has shown the benefits of randomisation functions, architects are left with the implausible task of selecting just one randomisation function to implement in a processor. Few papers provide help on this task. In [6, 7, 14, 15], the class of functions based on division of polynomials over GF (2) originally proposed for interleaved memories in vector processors [10] is promoted for use as set index functions for data caches. The performance of these functions in the presence of stride based access patterns can be shown ....

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N. Topham, A. Gonzalez, and J. Gonzalez. The design and performance of a conflict-avoiding cache. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 71--80, Dec. 1997.

....the past decade, extrapolations show that future processors will be able to access only small direct mapped caches (4 to 8 kB) in one or two clock cycles [2, 5] Such caches usually suffer from many conflict misses. By using a randomising set index function, conflict miss ratios can be reduced [6, 16, 21]. It was shown that the average miss ratio of the SPEC95 benchmark suite can be halved this way [21] There are many set index functions one can think of. Typically, one requires that the functions be cheap to evaluate, because they are in the critical path of the cache access. This condition ....

....caches (4 to 8 kB) in one or two clock cycles [2, 5] Such caches usually suffer from many conflict misses. By using a randomising set index function, conflict miss ratios can be reduced [6, 16, 21] It was shown that the average miss ratio of the SPEC95 benchmark suite can be halved this way [21]. There are many set index functions one can think of. Typically, one requires that the functions be cheap to evaluate, because they are in the critical path of the cache access. This condition holds for the functions that can be computed using only XOR gates. We will use these functions during ....

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N. Topham, A. Gonzalez, and J. Gonzalez. The design and performance of a conflict-avoiding cache. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 71--80, Dec. 1997.

....history and prediction logic. Consequently, if a designer is opting to use a victim cache, it may be worth considering adding in the extra hardware to convert it into a miss history driven victim cache if the resources are available. 3. 7 Conflict Avoidance or Reduction through Better Placement Topham et al. 1997] introduce a conflict avoiding cache architecture. Conventional caches suffer from repeated conflict misses as they do not use robust indexing functions. The authors propose that an irreducible polynomial modulus (I Poly) permutation function is 7 an ideal one for conflict resistant cache ....

Topham, N., Gonzalez, A., and Gonzalez, J. (1997). The Design and Performance of a Conflict-avoiding Cache. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture, pages 71--80, Research Triangle Park, North Carolina.

....primary section together with a secondary section of higher associativity. Some examples of schemes to improve performance of direct mapped caches are victim caches [1] hash rehash caches [2] column associative caches [3] MRU caches [4] half and half caches [5] conflict avoiding caches [6], and pollution control caches [7] A victim cache [1] is a small fully associative cache of typically no more than 16 blocks. If a block in the main direct mapped cache has to be replaced, that entry (called the victim) is transferred to the victim cache. The intent is that the next time there ....

....words, one half of the cache is direct mapped and the other half is associative. Theobald et al. found that in such a case where the assist cache is as big as the primary cache, the assist cache can simply be 2 way or 4 way set associative rather than fullyassociative. The conflict avoiding cache [6], is based on polynomial modulus functions and demonstrates that pseudo randomly indexed caches are effective in performance terms and practical from an implementation viewpoint. Pollution control caching from Walsh and Board [7] is another effort to improve performance of caches by controlling ....

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N. Topham, A. Gonzalez, J. Gonzalez, The design and performance of a conflict-avoiding cache, Proceedings of MICRO-30, Raleigh, NC, December 1997, pp. 71--80.

.... nonblocking caches [BK96] prefetch [CB92, MLG92,KK97] and speculative loads [RL92, Dul98] Reduction of conflicts without increasing associativity can be achieved both by placement strategies [KH92, CKSA98, CGM91] and by indexing schemes which are designed reduce the probability of conflicts [TGG97] All of these approaches can at best hide the latency of DRAM. Increasing associativity or faking the effect of increased associativity reduces misses and hence reduces the number of times that the latency of DRAM is an issue. Latency hiding techniques also reduce the number of times that ....

N. Topham, A. Gonzalez, and J. Gonzalez. The design and performance of a conflict-avoiding cache. In Proc. 30th Int. Symp. on Microarchitecture (MICRO30) , pages 71--80, Research Triangle Park, NC, 1 -- 3 December 1997.

....bits in A. This does not seriously degrade the quality of the mapping function. Ipoly mapping functions have been studied previously in the context of stride insensitive interleaved memories (see [17] 18] and have certain provable characteristics of significant value for cache indexing. In [24] it was demonstrated that a skewed Ipoly cache indexing scheme shows a higher degree of conflict resistance than that exhibited by conventional set associativity or other (non Ipoly) xor based mapping functions. Overall, the skewed associative cache using Ipoly mapping and a pure lru replacement ....

....programs with negligible conflict misses. The final cache organization shown in table II is the two way skewed associative cache proposed originally by Seznec [8] In its original form it used two bitwise xorindexing functions. Our version uses Ipoly indexing functions, as proposed in [10] and [24]. In this case two distinct Ipoly functions are used to construct two distinct cache indices from each address. Pure lru is difficult to implement in a skewed associative cache, so here we present results for an cache which uses a realistic pseudo lru policy (labelled plru) and a cache which uses ....

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N. Topham, A. Gonz'alez, and J. Gonz'alez, "The design and performance of a conflict-avoiding cache," in Proc. Int. Symp. on Microarchitecture, pp. 71--80, Dec. 1997.

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N. Topham, A. Gonz alez, and J. Gonz alez. The Design and Performance of a Conflict-Avoiding Cache. In Proc. of the 30th Annual International Symposium on Microarchitecture (MICRO-30), pages 71--80, Research Triangle Park, NC, Nov. 1997.

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