K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementations)," IEEE Trans. Computer-Aided Design, vol. 18, pp. 101--117, Jan., 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....another cube c 2 where the values of multiple variables may change during the transition. The cube c 1 is called the start cube and c 2 is called the end cube of the transition. The smallest cube that contains both c 1 and c 2 is called the generalized transition cube and is denoted [c 1 ; c 2 ] [25]. This cube includes all possible minterms that a machine may pass through starting in c 1 and ending in c 2 . A generalized transition cube can also be represented with a product which contains a literal for each variable x i in which c 1 (i) c 2 (i) 6= An open generalized transition cube [c ....

.... transition [c 1 ; c 2 ] for a function f is an extended burst mode transition if for every minterm m i 2 [c 1 ; c 2 ) f (m i ) f (c 1 ) and for every minterm m i 2 c 2 , f (m i ) f (c 2 ) Therefore, if a function only has extended burst mode transitions, then it is function hazard free [17, 25]. Although there are no functions hazards, there may be logic hazards. In order to design a hazard free SOP cover, we must consider each possible type of transition in turn. First, if during a static 1 1 transition [c 1 ; c 2 ] the cover of f can momentarily evaluate to 0, then there exists a ....

[Article contains additional citation context not shown here]

K. Y. Yun and D. L. Dill. Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementation) . IEEE Transactions on Computer-Aided Design, 18(2):101--117, Feb. 1999.

....data. In contrast to the priority and type bits, no logical operations are performed on data bits; thus less costly single rail domino logic suffices for the data crossbars. 4. 2 Control Datapath control consists of extended burst mode controllers [17] implemented as generalized C elements [18]. The routing decision is made at the crossbar as shown in Figure 7 and propagated from one data slice to the next so that a broadcast to all Y X Priority Comp X Y AX BX NX AY BY NY Xhigh Yhigh Decision Circuit Cross cross T cross F XBAR XBAR Data A B A B Priority AX ....

K. Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized C-elements. In Proc. European Design Automation Conference (EURO-DAC), pages 290--295, September 1996.

....instruction ready control (IR) waits for both the locally decoded length and the ByteRdy signal from neighboring columns downstream (for length ) before generating InstRdy for the TU. The BC circuit is shown in Fig. 11. Many FSMs such as the byte control were designed using the 3 D synthesis tool [13], 14] and optimized using the relative timing methodology [3] The actual circuits employ some pulsed signaling (TagAck is pulsed) and partial handshakes. Fig. 11. Byte control FSM. Req and Ack signals interface the FIFO to the BU. Once a tag arrives at the column (TagArrived in Fig. 9 is set) ....

K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementation)," IEEE Trans. Computer-Aided Design, vol. 18, pp. 101--117, Feb. 1999.

....(IR) waits for both the locally decoded length and the ByteRdy signal from L Gamma 1 neighboring columns downstream (for length L) before generating InstRdy for the TU. The Byte Control circuit is shown in Figure 11. Many FSMs such as the Byte Control were designed using the 3D synthesis tool [13], 14] and optimized using the Relative Timing methodology [3] The actual circuits employ some pulsed signaling (TagAck is pulsed) and partial handshakes. Once a tag arrives at the column (TagArrived in Figure 9 is set) the length decoder is notified (this signal is needed for handling prefixed ....

Kenneth Y. Yun and David L. Dill, "Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementation)," IEEE Transactions on Computer-Aided Design, vol. 18, no. 2, pp. 101--117, Feb. 1999.

....implemented using basic gates or complex gates. In this paper, we describe two ways of implementing the next state function: two level SOP and generalized C element (an efficient form of set reset logic implemented as a pseudostatic asymmetric complex gate, as depicted in Fig. 6) 33] 4] 17] [34]. The underlying theory for hazard free implementations is first developed for the two level SOP and then applied to the generalized C element. IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 6 f set f reset f f weak Fig. 6. A generalized C element with a ....

....OF INTEGRATED CIRCUITS AND SYSTEMS 13 functions are completely and correctly specified, i.e. functionhazard free. In this section, we present two different methods to implement hazard free next state logic: the two level AND OR implementation [43] and the generalized C element implementation [34]. d t = 0 t = d Pure delay model Inertial delay model Inverter Fig. 20. Delay models. The existence of hazards depends on the delay assumptions in the circuit model used and on the models of the delay itself. Many delay models have been proposed [19] 45] 46] here are two commonly used ....

[Article contains additional citation context not shown here]

K. Y. Yun, "Automatic synthesis of extended burst-mode circuits using generalized C-elements," in Proc. European Design Automation Conference (EURO-DAC), Sept. 1996, pp. 290--295.

....waits for both the locally decoded length and the ByteRdy signal from L Gamma 1 neighboring columns downstream (for length L) before generating InstRdy for the TU. The Byte Control circuit is shown in Figure 11. Many FSMs such as the Byte Control were designed using the 3D synthesis tool [13] [14] and optimized using the Relative Timing methodology [3] The actual circuits employ some pulsed signaling (TagAck is pulsed) and partial handshakes. Once a tag arrives at the column (TagArrived in Figure 9 is set) the length decoder is notified (this signal is needed for handling prefixed and ....

Kenneth Y. Yun and David L. Dill, "Automatic synthesis of extended burst-mode circuits: Part II (automatic synthesis)," IEEE Transactions on Computer-Aided Design, vol. 18, no. 2, pp. 118-- 132, Feb. 1999.

....(IR) waits for both the locally decoded length and the ByteRdy signal from L Gamma 1 neighboring columns downstream (for length L) before generating InstRdy for the TU. The Byte Control circuit is shown in Figure 11. Many FSMs such as the Byte Control were designed using the 3D synthesis tool [13], 14] and optimized using the Relative Timing methodology [3] The actual circuits employ some pulsed signaling (TagAck is pulsed) and partial handshakes. Once a tag arrives at the column (TagArrived in Figure 9 is set) the length decoder is notified (this signal is needed for handling prefixed ....

Kenneth Y. Yun and David L. Dill, "Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementation)," IEEE Transactions on Computer-Aided Design, vol. 18, no. 2, pp. 101--117, Feb. 1999.

....R1 L2 R2 Fig. 11. Control flow example for a two stage TC chain: R means ready to evaluate, E means evaluating, D means done evaluating, and P means precharging. C. 2 Extended Burst Mode Controllers The datapath control consists of a set of extended burst mode (XBM) controllers [12] [13] and C elements (used to AND two events) In Fig. 10(b) shaded boxes are XBM controllers and shaded circles are C elements. An extended burst mode specification [12] consists of a finite number of states, a set of labeled state transitions connecting pairs of states, and a start state. Fig. ....

K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: part II (automatic synthesis)," IEEE Transactions on ComputerAided Design of Integrated Circuits, vol. 18, no. 2, pp. 118--132, Feb. 1999.

....L1 FB1 R1 L2 R2 Fig. 11. Control flow example for a two stage TC chain: R means ready to evaluate, E means evaluating, D means done evaluating, and P means precharging. C. 2 Extended Burst Mode Controllers The datapath control consists of a set of extended burst mode (XBM) controllers [12], 13] and C elements (used to AND two events) In Fig. 10(b) shaded boxes are XBM controllers and shaded circles are C elements. An extended burst mode specification [12] consists of a finite number of states, a set of labeled state transitions connecting pairs of states, and a start state. ....

....C.2 Extended Burst Mode Controllers The datapath control consists of a set of extended burst mode (XBM) controllers [12] 13] and C elements (used to AND two events) In Fig. 10(b) shaded boxes are XBM controllers and shaded circles are C elements. An extended burst mode specification [12] consists of a finite number of states, a set of labeled state transitions connecting pairs of states, and a start state. Fig. 12(a) and Fig. 12(b) show the XBM specifications of the crossbar control, which has 3 inputs (SuccDone, PredDone, Done) and 2 outputs (Eval, Prech) and of the feedback ....

K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: part I (specification and hazard-free implementations)," IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 18, no. 2, pp. 101--117, Feb. 1999.

....signals. At the (non first byte) columns that do not receive the tag, the LDs may output the length code and the IRs may generate InstRdy. However, as soon as Preempt is received (after signaling ByteReady) the BU is reset. The control circuits in BU were designed using the 3D synthesis tool [5, 6] and optimized using the Relative Timing methodology [3] The actual circuit employs some pulsed signaling and partial handshakes. Length 1 Length 2 Length 7 TagArrived TagOut 7 TagOut 2 TagOut 1 TagIn 1 TagIn 2 TagIn 7 InstRdy XBRdy Figure 5: Byte Unit circuit 4. RAPPID test results ....

K. Y. Yun and D. L. Dill, Automatic synthesis of extended burst-mode circuits: part II (automatic synthesis), IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 118132, Feb. 1999.

....signals. At the (non first byte) columns that do not receive the tag, the LDs may output the length code and the IRs may generate InstRdy. However, as soon as Preempt is received (after signaling ByteReady) the BU is reset. The control circuits in BU were designed using the 3D synthesis tool [5, 6] and optimized using the Relative Timing methodology [3] The actual circuit employs some pulsed signaling and partial handshakes. Length 1 Length 2 Length 7 TagArrived TagOut 7 TagOut 2 TagOut 1 TagIn 1 TagIn 2 TagIn 7 InstRdy XBRdy Figure 5: Byte Unit circuit 4. RAPPID test results ....

K. Y. Yun and D. L. Dill, Automatic synthesis of extended burst-mode circuits: part I (specification and hazard-free implementations), IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 101-117, Feb. 1999.

....techniques, which was both laborintensive and sub optimal. This paper proposes the first known technique to optimize the average case performance of a popular form of asynchronous controllers called burst mode control circuits [22] The control circuits are specified in extended burst mode (XBM) [39] and implemented using a modified Huffman architecture [22] 36] 39] Each circuit consists of a combinational logic block with some outputs fed back to the inputs through delay elements. The XBM specification and an implementation of SCSI INIT SEND controller are shown in Fig. 1 as an ....

.... proposes the first known technique to optimize the average case performance of a popular form of asynchronous controllers called burst mode control circuits [22] The control circuits are specified in extended burst mode (XBM) 39] and implemented using a modified Huffman architecture [22] 36] [39]. Each circuit consists of a combinational logic block with some outputs fed back to the inputs through delay elements. The XBM specification and an implementation of SCSI INIT SEND controller are shown in Fig. 1 as an example. In each state, the circuit waits for a set of specified input ....

[Article contains additional citation context not shown here]

K. Y. Yun and D. L. Dill, "Automatic synthesis of extendedburst-mode circuits: part I (specification and hazard-freeimplementations)," IEEE Transactions on Computer-Aided Design, vol. 18, no. 2, pp. 101--117,Feb. 1999.

....area when compared to traditional techniques. We also believe that these technology mapping algorithms are applicable to other fundamental mode design styles, such as Nowick s UCLOCK method [23] Extensions of our approach to fundamental mode circuits implemented with generalized C elements [37] is an interesting area of future research. Using generalized C elements often increases the performance of the circuits, but their optimization would most likely involve handling hazard free sequential decomposition as well as transistor level delay analysis. Another possible direction for future ....

K. Y. Yun, "Automatic synthesis of extended burst-mode circuits using generalized C-elements," in Proc. European Design Automation Conference (EURO-DAC), Sept. 1996, pp. 290--295.

....translated into the language of the formal verification tool SMV [6] and their communication has been verified to be deadlock free and to adhere to the specified asynchronous protocol. The control circuits have been designed using a 3D design style, and implemented with generalized C elements [9] that have low latency. The control circuitry overhead was further minimized by using timing assumptions that effectively hide it in the delay of the datapath. These timing assumptions were validated using Mentor Graphics Accusim (SPICE) 4 Results We have completed the design and simulation ....

Kenneth Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized C-elements. In EURO-DAC'96, 1996.

....transitions in the input burst may appear in arbitrary temporal order; outputs may be generated in any order. 4.1. 2 Controller implementation style The controller specifications were implemented in an efficient but robust form of multiple input change circuits using the synthesis tool 3D gC [16]. Each output is typically implemented with a single generalized C element. As an example, the implementation of the MUL2 controller is shown in figure 10. This design style uses an efficient strategy for the insertion of state variables. In particular, state variables change concurrently with an ....

K. Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized C-elements. In Proc. European Design Automation Conference (EURO-DAC), pages 290--295, September 1996.

....select input, facilitating data dependent choice. A toggle element alternates between routing an input event to one of two outputs. We present improved generalized C element based implementations of the more complicated select and toggle elements obtained using the burst mode 3D synthesis systems [8, 7, 9]. We designed both the traditional implementations of these elements [4] and our implementations in the MOSIS 1:2 m CMOS process and simulated them under the worst case process corner with a 4.6V power supply and at 100 ffi C. Our designs demonstrated significant improvements in latency and ....

Kenneth Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized Celements, 1996. Submitted to a conference.

.... 1 G R1 r SR r SR R1 1 G reset 1 G 1 G Rr weak r SR r SR r SR weak Figure 7: PCC asynchronous finite state machine specification and implementation. The asynchronous finite state machine (see figure 7) is specified in burst mode [19, 18] and synthesized using the 3D gC synthesis tool [20]. This burst mode state machine has two inputs (R ae , G 1 ) and two outputs (R 1 , SR ae ) In state 0, when R ae rises, the machine raises R 1 and goes to state 1. In state 1, the machines waits for G 1 to rise; when it does, the machine lowers R 1 and raises SR ae concurrently and goes to state ....

Kenneth Y. Yun. Automatic synthesis of extended burstmode circuits using generalized C-elements. To appear in EURODAC-96.

....arrive in arbitrary temporal order. Outputs may be generated in any order, but the next set of compulsory edges from the next input burst may not arrive until the machine has stabilized. Synthesis We synthesized the above 4 phase micropipeline control circuit using the GC based synthesis method [25]. The synthesis algorithm assumes that the target implementation is a pseudo static asymmetric CMOS complex gate, known as generalized C element [12, 3, 15] The synthesis procedure consists of two steps: state assignment and logic implementation. The state assignment step ensures that every ....

Kenneth Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized C-elements, 1996. Submitted to a conference.

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K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: Part I (specification and hazard-free implementations)," IEEE Trans. Computer-Aided Design, vol. 18, pp. 101--117, Jan., 1999.

No context found.

K. Yun and D. Dill. Automatic synthesis of extended burstmode circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(2):101--132, feb. 1999.

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