K.Y. Yun, "Synthesis of Asynchronous Controllers For Heterogeneous systems", Stanford University, 1994, Ph.D. Thesis  Home/Search   Document Details and Download   Summary   Related Articles   Check

....computer aided design (CAD) and methodology most suitable for aggressive timed asynchronous circuit design. Initial designs and methods were based on the CAD available at that time. The circuits were specified and synthesized using speed independent (SI) or burst mode (BM XBM) methodologies [2] [4], as well as metric timed circuit design [5] We quickly discovered that many of the circuits that achieved our performance goals contained some form of timing assumptions either the fundamental mode assumption of burst mode or gate level metric timing. The performance was improved by studying ....

....against one of the circuits in terms of area and energy. A more complete modeling of some of these circuits and parameters can be found in [29] The circuit examples in this paper contain static and domino gates normally employing a single pMOS device. Asynchronous tools such as ATACS [5] 3D [4], 30] and Petrify [2] can typically synthesize set reset flops and the appropriate functions [Fig. 1(a) We can often apply technology mapping into single variable reset (equivalently set) functions and implement them using standard footed domino gates as in Fig. 1(b) When the reset variable ....

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K. Y. Yun, "Synthesis of asynchronous controllers for heterogeneous systems," Ph.D. dissertation, Stanford Univ., 1994.

....circuit. It requires the environment to be slow enough in applying the new input values so as to allow the circuit to stabilize after responding to the previous input. The most well known method associated with this approach is the one called Burst Mode (BM) circuit design, developed in [9] 3] [10]. The second approach, on the contrary, makes no assumptions about the delays of the environment, permitting some of the inputs to switch in response to changes in some of the circuit s outputs, without waiting for their complete stabilization. This model This work has been supported by a grant ....

Kenneth Yi Yun, Synthesis of Asynchronous Controllers for Heterogeneous Systems, Ph.D. thesis, Stanford University, Aug. 1994.

....It requires the environment to be slow enough in applying the new input values so as to allow the circuit to stabilize after responding to the previous input. The most well known method associated with this approach is the one called burst mode (BM) circuit design, developed in [9] 3] and [10]. The second approach, Manuscript received October 2, 2000; revised April 23, 2001. This work was supported by a grant from Intel Corporation to the University Politcnica de Catalunya, by ESPRIT ACiD WG Nr. 21949, and by Grant EPSRC GR M94366. This paper was recommended by Associate Editor L. ....

K. Y. Yun, "Synthesis of Asynchronous Controllers for Heterogeneous Systems ," Ph.D. dissertation, Stanford Univ., 1994.

....better but is only capable of producing cube exact solutions. The most time efficient tool to date is ESPRESSO HF [21] but it uses heuristic algorithms and thus cannot guarantee either literal or cube exact solutions. These minimizers are currently used to perform logic minimization in the 3D [22] and MINIMALIST [5] burst mode synthesis tools. The approach taken in this paper exploits standard synthesis techniques traditionally used for gate level speedindependent synthesis, namely state graph exploration and derivation of single cube covers [16, 1, 2, 11] In previous work, we ....

....configurations for the benchmarks presented in this paper. The runtime and literal comparisons shown in Table 4 contains the largest benchmarks that have been built in the burst mode community to date. The postoffice [3] cache ctrl [18] diffeq [23] cd player [9] pscsi [24] sscsi [19] xscsi [22], dram ctrl [19] and barcode [20] are all derived from real life designs. The burst mode controllers ack cdplayer, ack fibonacci, ack diffeq, ack barcode, ack gcd, and ackfactorial are generated automatically from a procedural language description by the high level synthesis framework ACK [12, ....

K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, Aug. 1994.

....of the circuit. It requires that the environment be slow enough in applying the new input values so as to allow the circuit to stabilize after responding to the previous input. The most well known method associated with this approach is the one called Burst Mode (BM) circuit design, developed in [19, 26]. The second approach, on the contrary, makes no assumptions about the delays in the environment, permitting it to switch some of the inputs in response to changes in some of the circuit s outputs, without waiting for their complete stabilization. This way of action is often called input output ....

Kenneth Yi Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994.

....transitions T with respect to a reference transition a#.It tells that from the point of view of a# the skew of firings times of transitions from T is negligible. This assumption can be viewed as a local fundamental mode of T with respect to a and hence as a generalization of burst mode machines [14, 17]. An example of the application of simultaneity assumption is discussed in Section 4.2. Assumptions relating only input events cannot be automatically generated from the circuit behavior and can be provided by the designer or generated from the implementation of the environment. 2.6 Next state ....

....RT circuit provides necessary timing information for the down stream tools. Timing aware state encoding allows area delay optimization of RT circuits. Relative timing presents a middle ground between clocked and asynchronous circuits, and is a fertile area for CAD development. Both burst mode[14, 17] and speedindependent specifications are at opposite extremes of a more general class of relative timing specifications. Ackowledgments We would like to thank Shai Rotem, Luciano Lavagno, Alex Kondratyev and Alexandre Yakovlev for their contributions in motivating this work and developing the ....

Kenneth Yi Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994.

....transitions T with respect to a reference transition a. It tells that from the point of view of a the skew of firings times of transitions from T is negligible. This assumption can be viewed as a local fundamental mode of T with respect to a and hence as a generalization of burst mode machines [14, 17]. An example of the application of simultaneity assumption is discussed in Section 4.2. Assumptions relating only input events cannot be automatically generated from the circuit behavior and can be provided by the designer or generated from the implementation of the environment. 2.6 Next state ....

....RT circuit provides necessary timing information for the down stream tools. Timing aware state encoding allows area delay optimization of RT circuits. Relative timing presents a middle ground between clocked and asynchronous circuits, and is a fertile area for CAD development. Both burst mode[14, 17] and speedindependent specifications are at opposite extremes of a more general class of relative timing specifications. Ackowledgments We would like to thank Shai Rotem, Luciano Lavagno, Alex Kondratyev and Alexandre Yakovlev for their contributions in motivating this work and developing the ....

Kenneth Yi Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994.

....whether asynchronous design could improve performance, we also wanted to find out which design styles and circuit families are most suitable for aggressive circuit design. We started with Speed Independent (SI) and Extended Burst Mode (XBM) specifications. However, existing synthesis tools [5, 17] yielded results that were less than satisfactory for critical paths. Next, we turned to timed design and employed a metric timing synthesis tool [9] The resulting circuits demonstrated improved performance but were still below our expectations. Therefore, we turned to aggressive manual design ....

....nonclocked domino gates employing a single pMOS device. Signal Description Example input signal underline input output signal output inverted (asserted low) over bar z rising transition up arrow a falling transition down arrow b# Table 1. Notation conventions Asynchronous tools such as 3D [17], ATACS [8] and Petrify [5] can typically synthesize set reset flops and the appropriate functions (Figure 1(a) We apply technology mapping into single variable reset (equivalently set) functions, and implement them using standard footed domino gates as in Figure 1(b) When the reset variable is ....

K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, Aug. 1994.

....with each crossbar, totaling 64 bits of packet data. In contrast to the priority and type bits, no logical operations are performed on data bits; thus less costly single rail domino logic suffices for the data crossbars. 4. 2 Control Datapath control consists of extended burst mode controllers [17], implemented as generalized C elements [18] The routing decision is made at the crossbar as shown in Figure 7 and propagated from one data slice to the next so that a broadcast to all Y X Priority Comp X Y AX BX NX AY BY NY Xhigh Yhigh Decision Circuit Cross cross T cross F ....

....L1 has finished evaluating. GammaOkToEvalL1 denotes that a falling transition on the wire that it labels indicates that it is okay to put L1 in evaluation mode. 4.2. 2 Extended Burst Mode Controllers The controllers are implemented as extended burst mode asynchronous finite state machines [17]. A state transition S i S j , from state i to state j is enabled by an input burst and is accompanied by an output burst (also enabled by the same input burst) An input burst consists of one or more terminating edges, denoted by Signal Gamma (Signal falling) or Signal (Signal rising) For ....

K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994.

....(SI, a.k.a. Quasi Delay Insensitive) design styles were not satisfactory for the critical path of the design due to area performance overhead [2, 3, 6, 7] ffl Extended Burst Mode (XBM) machines, synthesized by the 3D tool, showed improved performance due to the fundamental mode timing assumption [14]. However, restrictions on expressing concurrency limit the types of protocols that can be implemented using this style, and further timing assumptions are not allowed. ffl Timed circuits synthesis based on metric timing in the tool ATACS [8] produced circuits with improved performance, but the ....

Kenneth Yi Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994.

....2 Further, its Lisp implementation and slow algorithms for state minimization and logic minimization severely limit its usefulness. Finally, it does not allow fed back outputs, missing an opportunity to signicantly reduce implementation complexity. The 3D system, presented in [38] 40][39], also synthesizes two level implementations, but accepts extended burst mode specications a larger class of specications than either Uclock or Minimalist (at present) handle. Unlike Uclock, 3D uses fed back outputs; unlike Minimalist, their use is not an option: it is required. In contrast to ....

Kenneth Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994.

....to specify what is to be designed. Many methods have been proposed for the specification of asynchronous designs. Some, however, are restricted to the signal transition level, such as I nets [17] signal transition graphs [7] 16] change diagrams [26] asynchronous finite state machines [9] 22] [28], and state graphs [1] Some languages do exist which abstract the behavior of the design, but they use non standard languages such as communicating sequential processes (CSP) 14] Occam [5] and Tangram [4] Each of these specification methods is also designed for a particular design style and ....

K. Y. Yun, Synthesis of Asynchronous Controllers for Heterogeneous Systems, PhD thesis, Stanford University, 1994.

....logic description is mapped onto cells in a certain technology. In each step care must be taken not to introduce hazards [6] i.e. spurious glitches on output wires, and critical races, which can allow a machine to enter an undefined state. More detailed information can be found in [2] 4] and [7]. The resulting logic implementation of the pulse divider is given in Figure 5. A careful examination of this circuit reveals that no extra delay elements in the two feedback wires are necessary. in out Fig. 5. Implementation of a pulse divider The logical value at the output of the burst mode ....

K.Y. Yun, Synthesis of Asynchronous Controllers for Heterogeneous Systems, Ph.D. thesis, Stanford University, 1994.

.... applied this procedure to several examples and compared our results with designs produced using other asynchronous design methodologies including Beerel s speed independent method (SYN) 29] Lavagno s method which adds delay elements to remove hazards (SIS) 6] and Yun s burst mode method (3D) [32]. The results are tabulated in Table I. The first two examples (SEL and SEL2) are different versions of the controller for a port selector. We also synthesized a timed circuit implementation for the controller from the simple asynchronous MMU described in [33] The timing information for these ....

....other methods. The results show up to two orders of magnitude less states in the timed case. In fact, due to the large state space of the MMU example, SIS runs out of memory during synthesis. The last two examples are compared with the 3D method with the 3D specifications and results taken from [32] assuming a 0.3ns inverter delay in a 0:8 m CMOS process. For these designs, our timed circuits show about a 30 percent improvement in area (comparing literal count) and delay. The DRAM controller is of particular interest because it is typically implemented as a synchronous circuit. Since a DRAM ....

K. Y. Yun, Synthesis of Asynchronous Controllers for Heterogeneous Systems, Ph.D. thesis, Stanford University, 1994.

....cubes can be reduced. 6 Results and Conclusions The example circuits we present in this section were derived from a set of asynchronous sequential circuits. They represent the implementation of either a state variable or an output of a so called Asynchronous Burst Mode Finite State Machine [4]. In table 1 the results of a few of the largest examples are shown. In this table we compare the three way method with espresso. Both programs were compiled with the same compiler with the same options. The second column mentions the number of inputs, privileged cubes and required cubes in the ....

K.Y. Yun, Synthesis of Asynchronous Controllers For Heterogeneous systems, Stanford University, 1994, Ph.D. Thesis

....now the complete specification can be synthesized directly. The last two examples of a DRAM controller (DRAM) and the target send burst mode portion of a SCSI controller (TSBM) were originally specified using burst mode state machines in [17] The 3D specifi cations and results are taken from [21] assuming a 0.3ns inverter delay in a 0:8 m CMOS process. The results are tabulated in Table 3. First, we compared the literal counts (Lit) for the gate level circuits derived using the generalized C element (gC) technique and our standard C implementation techniques. Our results show only about a ....

K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, 1994.

....management, high peak power dissipation, worst case design requirements, etc. Many have been advocating asynchronous design as a possible solution to these problems. As a result, there have been many recent advances in asynchronous design techniques, particularly in the area of automated synthesis [1, 15, 4, 8, 10, 12, 13, 17]. There have been some attempts at real system designs employing asynchronous techniques as well [16, 2, 5, 7, 11] It is becoming increasingly clear that system designers recognize asynchronous design as a viable alternative to strictly syn This research was supported in part by a gift from ....

....part of asynchronous design is controller design, because of complex hazard avoidance requirements and its implications on performance of overall circuits. This paper focuses on the performance side of controller design, namely an efficient synthesis technique for extended burst mode circuits [19, 17, 20], which have proved to be practically useful and promised good performance. The new synthesis algorithm described in this paper is geared toward synthesizing high performance circuits for small to medium size extended burst mode specifications. Previous synthesis techniques for (extended) ....

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K. Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994. Technical Report CSL-TR-94-644.

....the circuit s outputs. Bounded delays of gates and wires in the circuit are used to determine an upper bound on the period the environment must wait for the circuit to stabilize. The literature contains a large volume of work on fundamental mode circuits, starting from Huffman, Unger and McCluskey [44, 45, 89, 70, 27, 83, 82, 99]. Timed circuits [79] are another class of practical asynchronous circuits that make use of bounded delay assumptions within the circuit and in the environment. This can lead to significant improvement in circuit complexity and performance compared to DI, SI or QDI circuits [78] However, as with ....

....problems, namely min max timing simulation, time separation of events in acyclic systems and time separation of events in cyclic systems. To demonstrate the practicality of the algorithms, they have been applied to several asynchronous systems, including a suite of 3D asynchronous benchmarks [99], and a complete asynchronous differential equation solver chip [101] ffl Min max timing simulation: A polynomial time algorithm has been proposed for computing bounds on signal propagation delays from each primary input to each gate in a combinational circuit. To improve the accuracy of ....

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K. Y. Yun. Synthesis of asynchronous controllers for heterogeneous systems. PhD thesis, Stanford University, 1994.

....the computation. The behavior in the final iteration must be analyzed separately, and is not addressed in this paper. Details of the Di Eq design are described in Yun et al. s paper [16] The control logic of Di eq is implemented using four distributed extended burst mode (XBM) controllers [43]: ALU1Ctrl, ALU2Ctrl, MUL1Ctrl and MUL2Ctrl. The controllers communicate with one another using a handshaking protocol that implicitly assumes safe timing bounds in signaling. Like synchronous systems, the control is responsible for generating ALU opcodes, multiplexer selects, register load ....

....Di Eq cycles through a deterministic sequence of states. To model a controller, we examine its state transition diagram. For each state transition S i S j , let I be the set of input transitions and O the set of enabled output transitions. XBM semantics require that all terminating transitions [43] in I must occur before the state transition is enabled, and all transitions in O are concurrently enabled once all terminating transitions in I have occurred. To model this behavior, we create a max type event, say m, and draw zero delay edges from the events representing the terminating ....

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K. Y. Yun, Synthesis of asynchronous controllers for heterogeneous systems, Ph.D. thesis, Stanford University, 1994.

....machine. Burst mode asynchronous finite state machines were first introduced by Davis et al. [20] and formalized by Nowick and Dill [21] 22] Burst mode machines have been implemented using a method developed at HP Laboratories called MEAT [23] the locally clocked method [22] the 3D method [24], and the UCLOCK method [25] A burst mode specification is a variation of a Mealy machine that allows multiple input changes in a burst fashion in a given state, when all of a specified set of input edges appear, the machine generates a set of output changes and moves to a new state. The ....

K. Y. Yun, Synthesis of Asynchronous Controllers for Heterogeneous Systems, Ph.D. thesis, Stanford University, Aug. 1994.

....and actual systems design [3, 7, 8, 12, 13, 14, 19, 20] However, for maximum acceptability, it is imperative to be able to synthesize circuits that work with existing systems, which are largely made out of synchronous components. One particularly promising design style is the extended burst mode [26, 27]. This paper describes a new synthesis algorithm for asynchronous controllers specified in extended burstmode [26, 27] This algorithm assumes the target implementation to be a combinational circuit with both Supported by the Semiconductor Research Corporation, Contract no. 93 DJ 205. y ....

....to synthesize circuits that work with existing systems, which are largely made out of synchronous components. One particularly promising design style is the extended burst mode [26, 27] This paper describes a new synthesis algorithm for asynchronous controllers specified in extended burstmode [26, 27]. This algorithm assumes the target implementation to be a combinational circuit with both Supported by the Semiconductor Research Corporation, Contract no. 93 DJ 205. y Supported by the EXACT project under the program ESPRIT 6143 of the European Commission z Supported by the NSF Young ....

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Kenneth Y. Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, 1994. Technical Report CSL-TR-94-644. 20

.... paper proposes the first known technique to optimize the average case performance of a popular form of asynchronous controllers called burst mode control circuits [22] The control circuits are specified in extended burst mode (XBM) 39] and implemented using a modified Huffman architecture [22] [36], 39] Each circuit consists of a combinational logic block with some outputs fed back to the inputs through delay elements. The XBM specification and an implementation of SCSI INIT SEND controller are shown in Fig. 1 as an example. In each state, the circuit waits for a set of specified input ....

....transitions, it toggles a set of output signals, referred to as an output burst. In addition, depending on the implementation style, the circuit may internally toggle a number of state signals either concurrently with output signals or in a separate state burst before or after the output burst [36]. For the machine to operate properly, the environment must obey the generalized fundamental modeconstraint which essentially states that the next input burst must arrive after the fed back signals have propagated deeply enough into the combinational logic block, in order to ensure that there are ....

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K. Y. Yun, "Synthesis of Asynchronous Controllers for Heterogeneous Systems," PhD dissertation, Stanford University, Dept. of Electrical Engineeering, Stanford University, Stanford, CA, Aug. 1994.

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K.Y. Yun, "Synthesis of Asynchronous Controllers For Heterogeneous systems", Stanford University, 1994, Ph.D. Thesis

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K. Y. Yun. Synthesis of asynchronous controllers for heterogeneous systems. Technical Report CSL-TR-94-644, Dept. of electrical engineering, Stanford University, 1994.

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K.Y. Yun, \Synthesis of Asynchronous Controllers for Heterogeneous Systems", Ph.D thesis, Dept. of Elec. Eng., Stanford University, Aug. 1994.

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