S.M. Nowick, M.E. Dean, D.L. Dill and M. Horowitz, \The Design of a High-Performance Cache Controller: a Case Study in Asynchronous Synthesis", Integration, the VLSI journal, vol.15, no. 3, pp.241-262, Oct. 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....respectively. 8] has developed grammars (not provably complete, see [9] to specify DI circuits that induce a syntaxdirected translation into a basic set of primitives. 10] uses most of Keller s primitives and some more complex primitives to compile process algebras into DI circuits. [11, 12, 13, 14] have devised practical syn thesis techniques, yet they impose several restrictions on the specification unrelated to delay insensitivity or speed independence and provide very limited means for composing and decomposing DI modules. An automatic compiler in [3] applies some area optimization ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz, "The design of a high-performance cache controller: a case study in asynchronous synthesis, " in Proc. Hawaii International Conf. System Sciences, vol. I, pp. 419-427, IEEE Computer Society Press, Jan. 1993.

....rather than small area, the minimizers are run in single output configurations for the benchmarks presented in this paper. The runtime and literal comparisons shown in Table 4 contains the largest benchmarks that have been built in the burst mode community to date. The postoffice [3] cache ctrl [18], diffeq [23] cd player [9] pscsi [24] sscsi [19] xscsi [22] dram ctrl [19] and barcode [20] are all derived from real life designs. The burst mode controllers ack cdplayer, ack fibonacci, ack diffeq, ack barcode, ack gcd, and ackfactorial are generated automatically from a procedural ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. Integration, the VLSI journal, 15(3):241--262, Oct. 1993.

....Switch If asynchronous designs are to be widely used, it is critical to identify application domains where asynchronous techniques are of practical interest and to demonstrate their potential advantages using real designs. The zero overhead divider [100] the high performance cache controller [67], the DCC error corrector [92] the asynchronous differential equation solver [107] and the different versions of the Amulet processor [29] constitute major steps in this direction. In this chapter, the design of an asynchronous packet switch is presented. A packet switch was chosen as a case ....

Steven M. Nowick, Mark E. Dean, David L. Dill, and Mark Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. Integration, the VLSI journal, 15(3):241--262, October 1993.

....of language constructs and hardware modules, and essentially serve to specify the interconnection of predefined modules to achieve a function described in software. As yet, they provide no support for dealing with efficiency or optimization issues, however. Several other synthesis techniques [Chu87, Men88, LMBSV92, NDDH93] have been devised to be more easily realized in practice by imposing several restrictions on the types of specifications allowed. These restrictions are unrelated to requirements for achieving delay insensitivity or speed independence, and the methods proposed provide little or no general ....

Steven M. Nowick, Mark E. Dean, David L. Dill, and Mark Horowitz. The design of a highperformance cache controller: a case study in asynchronous synthesis. In Proc. Hawaii International Conf. System Sciences, volume I, pages 419--427. IEEE Computer Society Press, January 1993.

....path. The four phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage. 1 Introduction Asynchronous designs have been successfully applied to control oriented applications (such as chip interfaces [21, 11] bus controllers [24] cache controllers [16], and network communication controllers [5, 10] This research was supported in part by a gift from Intel Corporation. y This research was funded in part by a Zumberge Research Fund for Assistant Professors at USC and a NSF Career Award. datapath components (such as adders [13, 9] ....

Steven M. Nowick, Mark E. Dean, David L. Dill, and Mark Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. Integration, the VLSI journal, 15(3):241--262, October 1993.

....than that of the STG, and that the state encoding is more flexible in the implementations. Burst mode specifications have been very useful in specifying large, practical controllers, such as a SCSI data transfer protocol controller [19] and an asynchronous high performance cache controller [16]. The main practical disadvantage is that it does not allow input transitions to be concurrent with output transitions. The input choice mechanism, albeit more flexible than the STG, is still primitive. For example, it cannot handle choices between two sets of concurrent events if one set is a ....

S. Nowick, M. Dean,D. Dill, and M. Horowitz.The design of a high-performance cache controller: a case study in asynchronous synthesis. In 1993 Hawaii International Conference on Systems Science.

....mode) The focus of this paper is on fundamental mode asynchronous circuits, such as burst mode machines. Burst mode methods have recently been applied to several large and real world design examples, including a low power infrared communications chip [19] a second level cache controller [26], an SCSI controller [41] a differential equation solver [42] and an instruction length decoder [4] An important challenge for any asynchronous synthesis method is the development of optimized CAD tools. In synchronous design, CAD packages have been critical to the advancement of modern ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz, "The design of a high-performance cache controller: A case study in asynchronous synthesis, " in Proceedings of the Twenty-Sixth Annual Hawaii International Conference on System Sciences. New York: IEEE Computer Society Press, vol. I, pp. 419--427.

....of much recent research activity. A number of methods have been developed for the design of hazard free controllers [5, 2, 6, 13] These methods have been applied to several large and realistic design examples, including a low power infrared communications chip [3] a second levelcachecontroller [7], and an implementation of a SCSI controller [12] An important aspect of these methods is the development of optimized CAD tools. In synchronous design, the development and implementation of CAD packages has been critical to the success of modern automated digital design. In asynchronousdesign, ....

S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz. The design of a highperformancecache controller: a case study in asynchronoussynthesis. In HICSS1993.

....mode) The focus of this paper is on fundamental mode asynchronous circuits, such as burst mode machines. Burstmode methods have recently been applied to several large and realistic design examples, including a low power infrared communications chip [19] a second level cachecontroller [26], a SCSI controller [41] a di#erential equation solver [42] and an instruction length decoder [4] This work was supported by NSF under Grant no. MIP 9501880 and by an Alfred P. Sloan Research Fellowship. The presented work is an extended version of two recent conference papers [37] 36] ....

S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. In Proceedings of the Twenty-Sixth Annual Hawaii International Conference on System Sciences, volume I, pages 419--427. IEEE Computer Society Press, January 1993.

....5 3 7 0 6 0 dme fast 5 3 10 0 7 0 dme fast opt 5 3 15 0 14 0 Table 5: Results of Algorithm PI to DHF PI. 11 Experimental Results. Our hazard free logic minimization program was run on a set of examples. The largest example is a cache controller having 20 inputs and 19 outputs (dean ctrl) [27]. The program was also run on two SCSI controller designs (oscsi ctrl and scsi ctrl) 31] The examples were generated from state machine specifications using the locally clocked synthesis method [25] Specifications were given in burst mode [29, 25] a notation to describe asynchronous Mealy ....

....[28] is complete. The algorithms have been incorporated into two other synthesis systems as well [38, 26] and can be used in a number of other sequential synthesis methods. The algorithms have also been applied to several substantial asynchronous designs, including a second level cache controller [27] and state machines for an infrared communications chip [1] 23 Acknowledgements. The authors would like to thank Professor Giovanni De Micheli for suggesting that we consider reducing prime implicants to dhf prime implicants. We thank Richard Rudell for clarifications about espresso exact and ....

S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. INTEGRATION, the VLSI journal, 15(3):241--262, October 1993.

....the arrival times of packets from the external ports and the PE can be completely random. In a synchronous system, these arrivals would have to be normalized to the system clock, resulting in slower delivery. Receptive asynchronous systems begin processing packets as soon as data arrives [NDDH93] This robustness of interfaces is also being investigated for commercial applications in noisy environments [MCS94] The low power nature of asynchronous architectures was one further advantage demonstrated in the Post Office. Asynchronous circuits contain fine grain, dynamic power management ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz. The Design of a High-Performance Cache Controller: A Case Study in Asynchronous Synthesis. Integration, the VLSI Journal, 15(3):241--262, October 1993. Special issue on asynchronous systems.

....are often easily met) but allow greater flexibility in the synthesis path. A number of tools have been developed for both burst mode [57] 65] 66] 67] 59] 68] and STG [69] 60] 70] 71] 72] 73] synthesis; these have been applied to a number of real world designs [74] 13] 8] [75], 73] 76] An alternative approach has also been proposed, called timed circuits [77] which incorporates user specified timing information to optimize the circuits. Compiling asynchronous circuits from higher level programming languages has been extensively explored in [78] 79] 80] and ....

S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz, "The design of a high-performance cache controller: a case study in asynchronous synthesis," INTEGRATION, the VLSI journal, vol. 15, no. 3, pp. 241--262, October 1993.

....cycle time were 3.3ns and 6.1ns. Comparison to locally clocked and UCLOCK methods. In Table V, we compare the 3D and two competing methods (locally clocked method [2] and UCLOCK method [18] for 6 controller implementations 4 including two large published examples, dramc [19] and cache ctrl [20]. It is interesting to compare to these methods, because (1) both locally clocked and UCLOCK methods use the burst mode as the user level specification formalism, which means that every machine synthesized using these methods can be re implemented in 3D, and (2) the locally clocked method has been ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz, "The design of a high-performance cache controller: a case study in asynchronous synthesis, " Integration, the VLSI journal, vol. 15, no. 3, pp. 241--262, Oct. 1993.

....of asynchronous state machine synthesis [24, 20, 33, 4, 18] Each method produces low latency machines which are guaranteed hazard free at the gate level. These methods have been automated and applied to some significant industrial examples: an adaptive routing chip [6] a cache controller [19], an infrared communications chip [1] and a SCSI controller [23] The design tools have benefited from a number of recent hazard free optimization algorithms: exact two level logic minimization [21] multi level logic optimization [29, 9, 11] technology mapping [27] and synthesis for testability ....

S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. In Proceedings of the Twenty-Sixth Annual Hawaii International Conference on System Sciences, volume I, pages 419--427. IEEE Computer Society Press, January 1993.

....exact two level synthesis method. We also give a detailed example of the specified path optimization. 1 Introduction There have been many recent advances in asynchronous circuits and systems, both in tool design [1, 2, 4, 6, 9, 11, 13, 15, 16, 17, 18, 23, 24, 25] and actual systems design [3, 7, 8, 12, 13, 14, 19, 20]. However, for maximum acceptability, it is imperative to be able to synthesize circuits that work with existing systems, which are largely made out of synchronous components. One particularly promising design style is the extended burst mode [26, 27] This paper describes a new synthesis ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. Integration, The VLSI Journal, 15(3):241--262, October 1993.

.... 19, 2, 30, 34, 15, 1] A number of methods have been developed for the design of hazard free controllers [22, 20, 37, 13, 27] These methods have been applied to several large and realistic design examples, including a low power infrared communications chip [14] a second level cache controller [21], a SCSI controller [35] a differential equation solver [36] and an instruction length decoder [4] An important aspect of these methods is the development of optimized CAD tools. In synchronous design, CAD packages have been critical to the advancement of modern digital design. In asynchronous ....

S.M. Nowick, M.E. Dean, D.L. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. In Proceedings of the Twenty-Sixth Annual Hawaii International Conference on System Sciences, volume I, pages 419--427. IEEE Computer Society Press, January 1993.

....flexible than that of the STG, and that the state encoding is more flexible in the implementations. Burst mode specifications have been very useful in specifying large, practical controllers, such as a SCSI data transfer protocol controller [54] an asynchronous high performance cache controller [51], and asynchronous communications controllers [37] Its main practical disadvantage is that it does not allow input changes to be concurrent with output changes. The input choice mechanism is more flexible than the STG but still primitive. For example, it cannot handle choices between two sets of ....

S. M. Nowick, M. E. Dean, D. L. Dill, and M. Horowitz. The design of a highperformance cache controller: a case study in asynchronous synthesis. Integration, The VLSI Journal, 15(3):241--262, October 1993.

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S.M. Nowick, M.E. Dean, D.L. Dill and M. Horowitz, \The Design of a High-Performance Cache Controller: a Case Study in Asynchronous Synthesis", Integration, the VLSI journal, vol.15, no. 3, pp.241-262, Oct. 1993.

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