Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, and Jelio T. Yantchev. High-level design of an asynchronous packet-routing chip. In Jrgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 261--274. Elsevier Science Publishers, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Research on asynchronous packet switches has not been as active. Although not entirely the same application, several asynchronous packet or message routing chips for multiprocessors have been designed and built. Examples are the Torus Routing Chip [15] and the Mesh Routing Chip [28] In [37], Josephs et al. presented an interesting high level design of an asynchronous packet routing chip. An algebraic formalism is used to specify its operation and for synthesis and verification. Yantchev and Nedelchev [103] also presented a packet switching device, designed as a delay insensitive ....

Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, and Jelio T. Yantchev. High-level design of an asynchronous packet-routing chip. In Jrgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 261--274. Elsevier Science Publishers, 1992.

....is that solutions can be constructed from components whose combinations have algebraic properties like those of the arithmetic building blocks which we used here. We are investigating, as an example, the derivation of routing circuits implemented as arrays of binary decisions and arbiters [12]. Acknowledgement. The work reported in this paper has been supported by grants from the UK Science and Engineering Research Council, and was done while Mary Sheeran held a Royal Society of Edinburgh BP Research Fellowship at the Department of Computing Science of the University of Glasgow. ....

Mark B. Josephs, Rudolph H. Mak, Jan Timen Udding, Tom Verhoeff and Jelio T. Yantchev, High-level design of an asynchronous packet routing chip, in [17].

.... a very simple ring communication network that was designed as a formal verification case study [15] Josephs et al. produced a hand proof that switching elements similar to those proposed for the INMOS Transputer could be connected together in a regular way to implement a router of arbitrary size [10]. We do not go into details of the formal specifications and proofs here. We concentrate on our experiences performing the verification. The time taken was comparable to the time originally spent designing, implementing and informally testing the fabric. No errors were found in the fabricated ....

Mark B. Josephs, Rudolph H. Mak, Jan Tijmen Udding, Tom Verhoeff, and Jelo T. Yantchev. High level design of an asynchronous packet-routing chip. In J. Staunstrup and R. Sharp, editors, Proceedings of the Second IFIP Workshop on Designing Correct Circuits , pp. 261--274, January 1992.

.... network that was designed as a formal verification case study [17] Josephs et al. produced a hand proof in a CSP like algebraic formalism that switching elements similar to those proposed for the INMOS Transputer could be connected together in a regular way to implement a router of arbitrary size [14]. The outline of the remainder of this report is as follows. In Section 2, we overview the Fairisle network. The purpose of this section is to illustrate the environment in which the switching fabric operates. In Sections 3 and 4, we informally describe the intended behaviour and implementation of ....

Mark B. Josephs, Rudolph H. Mak, Jan Tijmen Udding, Tom Verhoeff, and Jelo T. Yantchev. High level design of an asynchronous packet-routing chip. In J. Staunstrup and R. Sharp, editors, Proceedings of the Second IFIP Workshop on Designing Correct Circuits, pages 261--274, January 1992.

....as fast as the DETDFF design, requires much smaller area for data storage. 1 Introduction Asynchronous designs have been successfully applied to control oriented applications (such as chip interfaces [21, 11] bus controllers [24] cache controllers [16] and network communication controllers [5, 10]) This research was supported in part by a gift from Intel Corporation. y This research was funded in part by a Zumberge Research Fund for Assistant Professors at USC and a NSF Career Award. datapath components (such as adders [13, 9] multipliers [7] and dividers [20] as well as general ....

Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, and Jelio T. Yantchev. Highlevel design of an asynchronous packet-routing chip. In Jørgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 261--274. Elsevier Science Publishers, 1992.

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