R. H. Krambeck, C. M. Lee, and H. S. Law, "High-Speed Compact Circuits with CMOS", in IEEE Journal of Solid State Circuits, pp 614-619, Vol. SC-17, No. 3, June 1982.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....reduction for the largest circuit. Keywords Domino Logic, Delayed Clocks, Low power I. Introduction D YNAMIC logic circuits [5] are used in highperformance circuits due to their speed and area advantage over static CMOS circuits. One well known dynamic logic family is the domino CMOS family [2], which, however, su#ers from its inability to perform inversions. Various methods have been proposed to overcome this restriction. One such method is the dual output domino logic family [1] In the standard dual output domino logic gate [7] shown in Figure 1 each dual output gate consists of two ....

R. Krambeck, C. Lee, and H. Law, "High speed compact circuits with CMOS," IEEE Journal of Solid-State Circuits, vol. SC-17, no. 3, pp. 614--619, June 1982.

....self resetting domino circuits which resemble wave pipelined designs in their need for well matched delays. We use self resetting domino as the starting point for our designs presented in section 4. 2. 2 Self Resetting Domino Self resetting domino circuits [3] are a variation of domino circuits [6] where the precharge control signal for each gate is derived from the gate s output. As an example, figure 4 shows a self resetting domino, twoinput AND gate. Transistors pl andp2 are the precharge transistors. After precharge, node g is high. If the a and b inputs both go high, then node g is ....

R. Krambeck, C. Lee, and H. Law. High-speed compact circuits with CMOS. IEEE J. of Solid-State Circuits, SC- 17:614 619, June 1982.

....redundant number systems like Carry Save reduce evaluation time by avoiding carry propagation as long as we stay in the redundant number system. Beneath the algorithmic level, there are several possibilities on the logic level to speedup these data paths. The use of dynamic logic like Domino [1] ensures fastest evaluation because only N transistors realize the logic function (explained in section 2) The question and the main scope of this paper is how to realize such fast algorithms in dynamic logic in a power efficient way. As a realization for fastest evaluation with dynamic logic, ....

....5 shows comparisons and simulation results of a redundant adder row. 2. BASICS Comprehension of the pros and cons of dynamic logic, distinction between single and dual rail and the resulting inference for clocking schemes is fundamental and will be discussed briefly. Figure 1 shows Domino logic [1] and True Single Phase Clock (TSPC) logic [6] The dynamic principle is based on two phases controlled by a clock signal and can be explained for Domino as follows: during precharge phase (clock is low) the dynamic node is precharged to high and the output is reset to low. During evaluation phase ....

R. H. Krambeck, C. M. Lee and H.-F. S. Law, "High-Speed Compact Circuits with CMOS", Journal of Solid-State Circuits, IEEE, Vol. SC-17, No. 3, June 1982.

....redundant number systems like Carry Save reduce evaluation time by avoiding carry propagation as long as we stay in the redundant number system. Beneath the algorithmic level, there are several possibilities on the logic level to speedup these data paths. The use of dynamic logic like Domino [1] ensures fastest evaluation because only N transistors realize the logic function (explained in section 2) The question and the main scope of this paper is how to realize such fast algorithms in dynamic logic in a power efficient way. As a realization for fastest evaluation with dynamic logic, ....

....redundant adder row example and section 6 finishes with the summary. 2 Basics Comprehension of the pros and cons of dynamic logic, distinction between single and dual rail and the resulting inference for clocking schemes is fundamental and will be discussed briefly. Figure 1 shows Domino logic [1] and True Single Phase Clock (TSPC) logic [6] The dynamic principle is based on two phases controlled by a clock signal and can be explained for Domino as follows: during precharge phase (clock is low) the dynamic node is precharged to high and the output is reset to low. During evaluation phase ....

Krambeck, R. H., Lee, C. M., Law, H.-F. S.: High-Speed Compact Circuits with CMOS. Journal of SolidState Circuits, IEEE, Vol. SC-17, No. 3, June 1982.

....can be used. Because the synthesis and clock distribution is much easier in synchronous designs a single phase clock is desirable and therefore, an integration of self timed schemes in a synchronous structure combines fastest latch free evaluation with single clock behavior. DOMINO logic [1] is a simple realization of the dynamic idea but requires two clocking signals in minimum for pipelined designs (figure 1) For highest speed Harris et al. 2] published a latch free skew tolerant realization, where a scheme of overlapping clocking signals decreases sensitivity to clock slopes ....

R. H. Krambeck, C. M. Lee and H.-F. S. Law, "High-Speed Compact Circuits with CMOS", Journal of Solid-State Circuits, IEEE, Vol. SC-17, No. 3, Jun. 1982.

....HI skew static gates with wider than usual PMOS transistors [70] to speed the critical rising output during evaluation. Moreover, the static gates may perform arbitrary functions rather than being just inverters [74] All considered, domino logic runs 1. 5 2 times faster than static CMOS logic [42] and is therefore attractive enough for high speed designs to justify its extra complexity. 1. Don t confuse the word skew in HI skew gates with clock skew. BCD 18 1.4.2 Traditional Domino Clocking After domino gates evaluate, they must be precharged before they can be used in the ....

R. Krambeck, C. Lee, and H. Law, "High-Speed Compact Circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, 1982.

....reduction for the largest circuit. Keywords Domino Logic, Delayed Clocks, Low power I. Introduction D YNAMIC logic circuits [5] are used in highperformance circuits due to their speed and area advantage over static CMOS circuits. One well known dynamic logic family is the domino CMOS family [2], which, however, su#ers from its inability to perform inversions. Various methods have been proposed to overcome this restriction. One such method is the dual output domino logic family [1] In the standard dual output domino logic gate [7] shown in Figure 1 each dual output gate consists of two ....

R. Krambeck, C. Lee, and H. Law, "High speed compact circuits with CMOS," IEEE Journal of Solid-State Circuits, vol. SC-17, no. 3, pp. 614--619, June 1982.

....noise problems in wide input OR gates (especially with low transistor threshold voltage) In order to prevent this, a larger keeper transistor may be required which can have an impact on performance. Hence, the size of the keeper transistor should be selected carefully to optimise performance [3, 4]. a) Static CMOS b) Domino circuit c) Skewed CMOS with clock signal d) Skewed CMOS without clock signal Fig. 1) Width ratios of sizes of PMOS NMOS for each circuit style The circuit topology of a skewed logic is the same as that of the conventional static CMOS logic, however, the sizes of ....

R. Krambeck et al., "High--Speed Compact Circuits with CMOS," IEEE Journal of Solid State Circuit, vol. SC-17, no 3, pp. 614-619, June 1982

....logic blocks, giving added flexibility. As pointed out in Shoji [127] and discussed in section 3.6.4, this kind of circuit is extremely sensitive to noise. We use only n type precharged logic, connecting successive n type precharged gates with static inverters, in the style of Domino CMOS [74]. Figure 3.8 summarizes the NORA inversion parity rules developed in [52] that are used in our design style. There must be an even number of inverting gates between two C 2 MOS latches on different phases if only static gates are used. If either a single precharged gate or a series of ....

....adds only 8 transistors to each cell (Figure 4.4) The comparator consists of a dynamic XOR gate followed by an inverter whose output can pull down a pre charged match line which is shared by all the cells used for the match. These gates form a short chain of Domino CMOS logic, as described in [74, 127]. The comparator checks for equality between every slot in the IN row and the corresponding slot in the OUT row. As messages move to the right along the IN row they are compared with the messages in the OUT row below. If a match occurs, data from the IN row moves to the CHUTE. Comparison can be ....

R. H. Krambeck, C. M. Lee, and H. S. Law. High-speed compact circuits with CMOS. IEEE Journal of Solid-State Circuits, SC-17(3):614--619, June 1982.

....T ox , where T ox is the oxide thickness of each technology. Pseudo stuck at test sets can put all transistors in a CUT in the most effective stress condition. CMOS domino circuits are popular in speed critical designs because they switch faster and use smaller area than static CMOS circuits [Krambeck 82] Gronowski 96a] Choudhury 97] Jain 97] Researchers have studied testability of CMOS domino circuits. However, most previous work used transistor stuck on and stuck open models [Barzilai 84] Oklobdzija 84] Wunderlich 86] Jha 88] Jha 90] Bruni 92] Renovell and Figueras investigated I DDQ ....

Krambeck, R.H., et al., "High-Speed Compact Circuits with CMOS," IEEE J. of Solid-State Circuits, Vol. sc-17, No. 3, pp. 614-619, Jun., 1982.

....feedback using cross coupled static inverters does not function due to hard latching, but this is avoided by using dynamic logic. Precharged regenerative feedback repeaters have been used to reduce the delay of memory word lines [4] and carry chains [5] 6] Fig. 4(a) shows a Domino buffer [7] with its output connected back to its input. When the precharged node is pulled below the threshold voltage of the inverter, the low level is enforced locally. When added to a chain of switches as in Fig. 3, these circuits rapidly propagate a falling transition. By using a gated clock, as shown ....

R. Krambeck, C. Lee, and H.-F. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614--619, June 1982.

....processes by expressing cycle time in terms of the delay of a fanout of four (FO4) inverter, i.e. an inverter driving a load that is four times its input capacitance. Today s fastest microprocessors are operating at cycle times below 18 fanout of four inverter delays [1] 1 Domino circuits [2] are an important enabler for this cycle time improvement [3] 5] At such short cycle times, however, clocking overhead which was once negligible becomes a significant fraction of the clock period. As we will see in Section II, when domino circuits are pipelined in the same way that two phase ....

R. H. Krambeck, C. M. Lee, and H. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, pp. 614--619, June 1982. HARRIS AND HOROWITZ: SKEW-TOLERANT DOMINO CIRCUITS 1711

....being employed. In the past, we have proposed an information theoretic framework [5, 6] that enables us to determine these lower bounds in a rigorous manner. Past work [6] has determined these lower bounds for static circuits. In this paper, we consider dynamic circuit techniques such as domino [7] and noise tolerant domino [3] In particular, we compare the energy efficiency bounds for conventional domino and noise tolerant domino circuit techniques and determine to what extent noise immunity needs to be enhanced before the energy overhead starts to dominate. It is known that ....

R. H. Krambeck, C. M. Lee, and H.-F. S. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. 17, pp. 614-619, June 1982.

....Vout will be discharged while Vout stays at Vdd . Node B will converge to a lower voltage level due to charge sharing with node C. Note that in both cases the small glitch at the non switching output can be reduced by the output inverter. In comparison with the existing circuit techniques [14] [15], the proposed BS technique has the following features: The BS technique significantly improves the noiseimmunity. Clearly, noise pulses may impair the outputs of a BS gate when all the inputs are high during the precharge phase and at the beginning of evaluate phase when the SA starts latching. ....

R. H. Krambeck, C. M. Lee, and H.-F. S. Law, "Highspeed compact circuits with CMOS," IEEE J. SolidState Circuits, vol. 17, pp. 614-619, June 1982.

....Since the computation of the prefix sums of a large array of binary numbers, say N 2 14 is not very realistic, we assume that N 2 14 . Under this assumption, our simulation results show that our processor is at least 50 faster than any processor known to us, including the tree of adders [3], or the processor with the same structure as ours but with each shift switch replaced by a half adder (half adder based processor for short) Since each nMOS transistor based shift switch is about 70 of a half adder, the total area can be specified as 0:7 (N p N) A h , where A h is a ....

R. H. Krambeck, C. M. Lee, and H.S. Law, HighSpeed Compact Circuits with CMOS, IEEE Journal of Solid-State Circuits, SC-17, No. 3, June, 1982.

....1991. Gars93]Garside J.D. CMOS VLSI Implementaion of an Asynchronous ALU. Proceedings of the IFIP working conference on Asynchronous Design Methodologies, Manchester, England, 1993. Gonc83]N. F. Goncalves, H. J. De Man, NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures . [Kram82]R. H. Krambeck, C. M. Lee, H. S. Law. High Speed Compact Circuits with CMOS , IEEE J. Solid State Circuits, vol SC 17, pp. 614 619, June 1982. Liu93]Liu D. Svensson C. Trading Speed for Low Power by Choice of Supply and Threshold Voltages. IEEE Journal of Solid State Circuits. Vol 28 1, Jan. ....

....be difficult to use with some low power techniques in the synchronous framework, such as frequency management and or clock gating, since data may be lost or corrupted if the logic is not clocked and thereby refreshed regularly. The most commonly used dynamic logic styles are Domino (figure 1a) [Kram82], NORA[Gonc83] or a combination of the two (figure 1b) since cascading of stages is accommodated using one clock edge to drive the precharge signal. In Domino logic this is allowed since the output of the inverter is driven low during precharge. In further cascaded stages the n channel precharge ....

R. H. Krambeck, C. M. Lee, H. S. Law. "High-Speed Compact Circuits with CMOS", IEEE J. Solid-State Circuits, vol SC-17, pp. 614-619, June 1982.

....of a DSP chip. The aim of the work presented in this paper is to develop a low power multiplier targeted to asynchronous DSP systems. The technique is also applicable to synchronous systems if low power is of crucial importance. For low power operation, dynamic logic (such as domino logic [1]) inherently offers some advantages. In particular its reduced switched capacitance means that circuit activity draws less energy from the supply. Furthermore, since each output can undergo, at most, one transition per evaluation, spurious transitions, which in certain circuits can account for ....

R. Krambeck, C. Lee and H.F. Law, "High speed compact circuits with CMOS", IEEE Journal of Solid-State Circuits, vol. SC-17, pp.614-619, 1982.

....tracks one has available and the number of tracks required by the chosen topology, one uses either single ended or complementary signal circuits. Single ended signals include both the static or pass transistor logic families [10] While the fast complementary signal circuits include the domino [11], NORA [12] and CVSL [13] logic families. An expanded discussion about the merits and disadvantages of each logic family when implementing counters can be found in Song[14] For the topologies chosen, higher order arrays were implemented in domino logic, while all other topologies used a ....

R. Krambeck, C. Lee and H-F. Lew, "High Speed Compact Circuits with CMOS", IEEE Journal of Solid State, pp. 614-618, June 1982.

....tracks one has available and the interconnection requirements of the structure chosen, one uses either single ended or complementary signal circuits. Single ended signals include both the static or pass transistor logic families [9] While complementary signal circuits include both the domino [10], NORA[11] and CVSL[12] logic families. The static logic uses NMOS and PMOS transistor trees. These trees are never simultaneously active in steady state, and have no steady state power dissipation. The pass transistor logic family uses NMOS or NMOS PMOS transistors for steering the input to the ....

R. Krambeck, C. Lee and H-F. Lew, "High Speed Compact Circuits with CMOS", IEEE Journal of Solid State, pp. 614-618, June 1982.

....practical relevance of the methods. Index Terms Modeling, timing verification. I. INTRODUCTION H IGH performance microprocessors employ advanced circuit techniques to help meet their performance objectives. Critical sections of the design are often implemented in dynamic logic. Domino logic [4], 16] a popular style of dynamic logic, has the advantage of small area and fast operation over complementary static logic. However the use of domino logic has been restricted mainly to full custom designs, in part because of the difficulty of verification. Not only do electrical effects such as ....

....static timing verification for sequential circuits implemented in a mix of static and dynamic logic. We consider two popular styles of dynamic logic: regular domino logic, and a variant of domino logic called footless domino. The characteristic timing constraint for domino gates was stated in [4]: All nodes can make at most only a single (rising) transition and then must stay there until the next precharge. Most work in static timing analysis of sequential circuits has not considered dynamic logic. Also, most work on timing verification of dynamic logic has concentrated on the timing ....

R. H. Krambeck, C. M Lee, and H.-F. S. Law, "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. 17, no. 3, pp. 614--619, June 1982.

....respectively over dual output domino and a 48 power reduction for the largest circuit. 1 Introduction Dynamic logic circuits [5] are used in high performance circuits due to their speed and area advantage over static CMOS circuits. One well known dynamic logic family is the domino CMOS family [2], which, however, suffers from its inability to perform inversions. Various methods have been proposed to overcome this restriction. One such method is the dual output domino logic family [1] In the standard dual output domino logic gate [7] shown in Figure 1 each dual output gate consists of two ....

R. Krambeck, C. Lee, and H. Law, "High speed compact circuits with CMOS," IEEE Journal of Solid-State Circuits, vol. SC-17, no. 3, pp. 614--619, June 1982.

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R. H. Krambeck, C. M. Lee, and H. S. Law, "High-Speed Compact Circuits with CMOS", in IEEE Journal of Solid State Circuits, pp 614-619, Vol. SC-17, No. 3, June 1982.

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R.H. Krambeck, C.M. Lee, and H.S. Law. High-speed compact circuits with CMOS. IEEE J. of Solid-State Circuits, SC-17:614--619, June 1982. 14

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R. Krambeck, C. Lee, and H. Law. High-speed compact circuits with CMOS. IEEE J. of Solid-State Circuits, SC17: 614--619, June 1982.

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R. H. Krambeck, C. M. Lee, and H.S. Law, High-Speed Compact Circuits with CMOS, IEEE Journal of Solid-State Circuits, Vol SC-17, No. 3, June, 1982.

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