S.S. Pinter, "Register allocation with instruction scheduling: A new approach," Proc. ACM SIGPLAN Conf. Prog. Lang. Des. & Impl. (PLDI), pp. 248-257, June 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....to 64) We experimented 720 DAGs where the number of of nodes goes up to 400 and the number of values goes up to 380. Full results are detailed in [16, 14] 7. RELATED WORK Combining code scheduling and register allocation in DAGs has been studied in many works. All the techniques described in [10, 4, 13, 5, 12] use their heuristics to build an optimized schedule without exceeding a certain limit of values simultaneously alive in order to keep these values in physical registers. Our work is an extension to the URSA framework presented in [3] The minimum killing set technique tries to saturate the ....

Schlomit S. Pinter. Register Allocation with Instruction Scheduling: A New Approach. SIGPLAN Notices, 28(6):248--257, June 1993.

....of the technique have been proposed, to take register classes into account during graph coloring [68] 70] Furthermore, the graph coloring approach assumes that the live range of each value is known beforehand. Recent papers investigate the interaction between register allocation and scheduling [71], 72] 2) Data Routing: The above mentioned extension of graph coloring toward heterogeneous register structures has been applied to general purpose processors, which typically have a few register classes (e.g. floating point registers, fixed point registers, and address registers) DSP and ....

S. Pinter, "Register allocation with instruction scheduling: A new approach," SIGPLAN Notices, June 1993.

....again to minimize the insertion of spill code, both through careful analysis of register pressure, and by adding serializing edges to each basic block data dependency DAG. It is basic block based. An early attempt at combining register allocation with instruction scheduling was proposed by Pinter [16]. That work is based on an instruction level register based intermediate code, and is preceded by a phase to determine data dependencies. This dependence information then drives the allocator, generating a Parallelizable Interference Graph to suggest possible register allocations. Further, the ....

Pinter, S. S. Register allocation with instruction scheduling: A new approach. In Proc. ACM SIGPLAN Conference on Prog. Lang. Design and Implementation (Albuquerque, NM, June 1993), pp. 248--257.

....necessary to expose enough instruction level parallelism even at the expense of increasing the register pressure and, to some extent, the amount of spill code generated. Integrated techniques that try to minimize register spills while focusing on exposing parallelism were found to perform well [6, 5, 27, 29, 31]. All these approaches work on a given instruction sequence and attempt to improve register allocation and or instruction scheduling. In contrast, our MRIS approach generates an instruction sequence from a DDG where the precise order of instructions is not yet fixed. Modern out of order issue ....

S. S. Pinter. Register allocation with instruction scheduling: A new approach. In Proc. of the ACM SIGPLAN '93 Conf. on Programming Language Design and Implementation, pages 248-- 257, Albuquerque, NM, June 23--25, 1993.

....Later on some of the interference graph edges may be removed to aid in coloring and reducing spilling, at the cost of adding additional edges to the dpg. Pinter s work combines information from a modified form of dpg, and the register interference graph, to create the parallel interference graph [19]. First the transitive closure of the dpg is taken, and all edges become undirected. Then, edges are added between operations that have a resource constraint imposed by the architecture. Edges in the complement of this graph, represent operations that could be run in parallel. This new ....

Schlomit S. Pinter. Register allocation with instruction scheduling: A new approach. SIGPLAN Notices, 28(6):248--257, June 1993. Proceedings of the ACM SIGPLAN '93 Conference on Programming Language Design and Implementation.

....solved by forcing the callee to do the job: the saves and restores are added to an entry and exit basic block and are compacted after register assignment. This implies that local scheduling is used for these blocks. In another approach, Pinter introduces the Parallel Interference Graph (PIG) in [62] to exclude false dependences resulting from register allocation before scheduling. It works for local or global scheduling: in the latter case, extra edges have to be used to model control ow dependences. The PIG has as its nodes symbolic registers, as generated by the compiler in previous code ....

....can be executed in parallel will be connected. Since every node in the inverted graph corresponds to one symbolic register, we can take the union of this graph and the interference graph. This way, the resulting PIG yields a graph coloring without any false dependences. Pinter proves this in [62]. After the register coloring and assignment, an o the shelf scheduler can be used. Although one phase precedes another completely in this approach, the combination of data structures used in both traditional phases results in better scheduling possibilities. At the same time Pinter developed ....

Pinter, S. Register allocation with instruction scheduling: A new approach. In Proceedings of the ACM SIGPLAN'93 Conference on Programming Language Design and Implementation (June 1993), pp. 248-257.

....simultaneously alive than the amount of physical registers. Spill code dramatically decreases the performance because of memory hierarchy access latencies. A best approach is combining code scheduling under resource constraints. The relation between the two phases are studied in a lost of work [Bra94, GH88, BEH91, Pin93]. Their purpose is to try constructing a schedule with a limited amount of values simultaneously alive in order to avoid spill code when allocating registers. The main problem with such an approach is its high complexity. Only code scheduling problem under resource constraints is NP complete. ....

....The first one consists in putting a limit on values simultaneously alive within basic blocs; the second is driven by the register allocation where it estimates a scheduling cost to assign registers to values; the last uses a pre analysis to estimate the limit used in the first solution. In [Pin93], the author needs a first schedule to build a parallelizable interference graph. She proves that an optimal coloring (with a number of colors do not exceed the amount of registers) of this graph leads to an optimal register allocation without introducing false dependencies. In [Bra94] the author ....

Schlomit S. Pinter. Register Allocation with Instruction Scheduling: A New Approach. SIGPLAN Notices, 28(6):248--257, June 1993.

....schemes [21] Operation driven version of the CARS algorithm is motivated by this work. However, unlike their scheme, we switch to operation driven scheduling only for scheduling inter cluster copy OPs. Bradlee et al. [3] proposed a variation of the Goodman Hsu scheme and another technique. Pinter [46] proposed a technique that incorporates scheduling constraints into the interference graph used by graph coloring based allocators. Berson et al. [2] proposed a technique based on measuring the resource requirement first and then using that information for integrating register allocation in local ....

S. S. Pinter. Register allocation with instruction scheduling: A new approach. SIGPLAN Notices, 28(6):248--257, June 1993.

....schemes [30] Operationdriven version of the cars algorithm is motivated by this work. However, unlike their scheme, we switch to operation driven scheduling only for scheduling inter cluster copy OPs. Bradlee et al. [31] proposed a variation of the Goodman Hsu scheme and another technique. Pinter [32] proposed a technique that incorporates scheduling constraints into the interference graph used by graph coloring based allocators. Berson et al. [33] proposed a technique based on measuring the resource requirement first and then using that information for integrating register allocation in local ....

S. S. Pinter, "Register allocation with instruction scheduling: A new approach," SIGPLAN Notices, vol. 28, pp. 248--257, June 1993. Proceedings of the ACM SIGPLAN '93 Conference on Programming Language Design and Implementation.

....necessary to expose enough instruction level parallelism even at the expense of increasing the register pressure and, to some extent, the amount of spill code generated. Integrated techniques that try to minimize register spills while focusing on exposing parallelism were found to perform well [5, 3, 17, 19, 21]. All of the above approaches work on a given instruction sequence and attempt to improve register allocation and or instruction schedule. In contrast our MRIS approach, generates an instruction sequence from a DDG where the precise order of instructions is not yet fixed. Benchmark Loads Stores ....

S. S. Pinter. Register allocation with instruction scheduling: A new approach. In Proc. of the ACM SIGPLAN '93 Conf. on Programming Language Design and Implementation, pages 248--257, Albuquerque, NM, June 23--25, 1993.

....by register allocation may introduce artificial data dependencies that limit parallelism. Many authors have tackled this difficult problem, either by systematic experiments [2, 3] or by more theoretical considerations on respective influence of scheduling and register allocation on each other [4, 5], or by heuristics [6, 7] In a previous paper, Eisenbeis et al. have suggested an exact Integer Linear Programming (ILP) formulation for managing register allocation and instruction scheduling in a common framework. Their work applies only to basic blocks composed of forests of unary binary ....

S. S. Pinter. Register allocation with instruction scheduling. In Proceedings of 1993 SIGPLAN Conference on Programming Languages Design and Implementation, pages 248-- 257, Albuquerque, New Mexico, June 1993.

.... or II) and schedule the loop again [2] Recent experiments have demonstrated that this approach may never converge [3] Scheduling followed by register allocation may require much spill code [4] On the contrary, register allocation followed by scheduling may reduce the potential parallelism [5]. In this paper, we will show that scheduling followed by register allocation may obtain optimal results in most cases. The rest of the paper is organized as follows: Section 2 presents the formalism to represent a loop and a schedule. Section 3 shows three different lower bounds on the number of ....

S. Pinter. Register allocation with instruction scheduling. ACM SIGPLAN Notices, 28(26):248--257, 1993.

.... problem is further aggravated by the fact that schedules exhibiting high concurrency generally result in higher register requirements as well; consequently, a significant body of research has sought scheduling algorithms that result in high performance and low register requirements [14] 43] 49] 58][75]. This problem is crucial to the performance of future machines as higher levels of parallelism inherently exacerbate the register requirements [64] In this dissertation, we address the issue of register sensitive schedulers in the context of software pipelined loops. First, our research aims to ....

....by adding scheduling edges in the dependence graph to enable advantageous bundles. In this scheme, additional scheduling edges would supply some further temporal constraints on the subsequent scheduling. Some edges are guaranteed not to actually constrain the scheduler, as shown by Pinter [75]. Others, however, may constrain the scheduler. In the context of modulo scheduled loops, the danger of this approach resides in the fact that adding scheduling edges may, if not carefully applied, overly constrain the schedule of predicated blocks and may thus result in schedules with increased ....

S. S. Pinter. Register allocation with instruction scheduling: a new approach. Proceedings of the ACM SIGPLAN'93 Conference on Programming Language Design and Implementation, pages 248--257, June 1993.

....performed first register allocation or scheduling the first phase makes its decisions without considering the impact on the subsequent phase. An strategy for attempting to find a near optimal scheduling with a viable allocation is to perform simultaneous scheduling and register allocation [Pin93] The essence of the idea is that each time an operation is scheduled, an available register is allocated to hold the result. Also, if this operation is the last one to use a source register, the register is made available once again. When there are no available registers for holding the result ....

....schedules without increasing the register requirements of new variables too much. Finally, we also plan to investigate software pipelining with simultaneous register allocation and spilling. Scheduling with register allocation has been performed in the context of local scheduling [GH88, BEH91, Pin93] and more recently in the context of global acyclic scheduling [BGS94] but, to the best of our knowledge, not in the context of cyclic scheduling. 8.2.7 Improving the Sacks Register File Organization In the sacks register file organization, we have seen that self conflicting variables caused ....

S.S. Pinter. Register allocation with instruction scheduling. In Proc. of the 1993 ACM SIGPLAN Conf. on Programming Languages Design and Implementation, pages 248--257, June 1993.

....is adequate. Register assignment and instruction scheduling are effectively merged by doing them simultaneously. False dependences do not arise because instruction scheduling is done early and although spill code will be encountered, it will hopefully be in less crucial traces. Pinter s work [17] realizes that the register interference graph for early register assignment has fewer edges, thus allowing extraneous anti dependences to occur. This, in turn, leads to a schedule that is too conservative. To avoid this, her algorithm creates a parallelizable interference graph. To generate such ....

S. S. Pinter. Register allocation with instruction scheduling: A new approach. Proceedings of the ACM SIGPLAN '93 Conference on Programming Language Design and Implementation, pages 248--257, 1993.

....heuristics have been proposed to solve register allocation and instruction scheduling together. For example, the strategy used in [6, 8, 23] is to keep the information on the next use of each register. The register whose next use is the farthest is spilled if there are not enough registers. In [22], a graph combining the control data flow graph and the register interference graph was proposed to solve the two optimizations simultaneously. The problem with this approach is that one cannot determine the edges in the complement graph of the parallel interference graph if we have more than ....

S.S. Pinter, Register Allocation with Instruction Scheduling: a New Approach, Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 258-257, (1993).

....by register allocation may introduce artificial data dependencies that limit parallelism. Many authors have tackled this difficult problem, either by systematic experiments [2, 3] or by more theoretical considerations on respective influence of scheduling and register allocation on each other [4, 5], or by heuristics [6, 7] In a previous paper, Eisenbeis et al. have suggested an exact Integer Linear Programming (ILP) formulation for managing register allocation and instruction scheduling in a common framework. Their work applies only to basic blocks composed of forests of unary binary ....

S. S. Pinter. Register allocation with instruction scheduling. In Proceedings of 1993 SIGPLAN Conference on Programming Languages Design and Implementation, pages 248--257, Albuquerque, New Mexico, June 1993.

.... Word (VLIW) and superscalar machines [1, 2, 3] Software pipelining has been proposed for exploiting ILP within loops, which can effectively overlap the execution of operations from different iterations [4, 5, 6, 7, 8, 9, 10, 11, 12] Register Allocation is another key compilation issue [13, 14, 15, 16, 17]. It has been well known that performing register allocation before software pipelining may introduce unacceptable anti dependences due to the reuse of registers, which may limit software pipelining [17, 3] On the other hand, if software pipelining is done before register allocation, more ....

....jian mips.complang.tuwien.ac.at; Tel: 43 1 588014474; Fax: 43 1 5057838. z Dr. Eisenbeis is with INRIA Rocquencourt, Domaine de Voluceau, BP 105 78153, Le Chesnay Cedex, France. 1 The interaction between register allocation and loop free code scheduling has been studied since the mid 1980s [10, 18, 13, 16, 19], and register allocation for software pipelined loop has been studied by many researchers and some efficient techniques have been proposed [20, 12, 17, 15] However, the interaction between register allocation and software pipelining was lately considered in few studies. Mangione Smith, et al. ....

S. S. Pinter. Register allocation with instruction scheduling: A new approach. In proceedings of ACM SIGPLAN PLDI, 1993. 12

....slack scheduling, is a slight modification of the modulo scheduling software pipelining algorithm [GL86] Slack scheduling turns out to be optimal in most cases on the Cydra architecture [RYYT89] Two recent studies examine the relationship between register and functional unit constraints. Pinter [Pin93] proposes to modify the interference graph to prevent operations that can be run in parallel to use the same register. Berson et al. BGS93] reducess the problem of resource with register allocation to finding independent chains of operations in the DAG. 4 To our knowledge, no work has been done ....

S.S. Pinter. Register allocation with instruction scheduling. In Proceedings of 1993 SIGPLAN Conference on Programming Languages Design and Implementation, pages 248--257, Albuquerque, New Mexico, June 1993.

No context found.

S. S. Pinter. Register allocation with instruction scheduling: a new approach. In SIGPLAN '93 Conference on Programming Language Design and Implementation, pp. 248#257, ACM, June 1993.

No context found.

S.S. Pinter, "Register allocation with instruction scheduling: A new approach," Proc. ACM SIGPLAN Conf. Prog. Lang. Des. & Impl. (PLDI), pp. 248-257, June 1993.

No context found.

Schlomit S. Pinter. Register allocation with instruction scheduling: A new approach. In Proceedings of the ACM SIGPLAN '93 Conference 111 on Programming Language Design and Implementation, pages 248-- 257, Albuquerque, New Mexico, June 23--25, 1993. SIGPLAN Notices, 28(6), June 1993.

No context found.

S.S. Pinter, "Register Allocation with Instruction Scheduling: A New Approach," Proc. ACM SIGPLAN '93 Conf. Programming Language Design and Implementation, pp. 248-257, June 1993.

No context found.

S. S. Pinter. Register Allocation with Instruction Scheduling: A New Approach. SIGPLAN Notices, 28(6):248--257, June 1993.

No context found.

S. Pinter. 1993. "Register allocation with instruction scheduling: A new approach", Proc. ACM SIGPLAN' 93 Conference on Programming Language Design and Implementation, Dec., pp. 248-257.

First 50 documents  Next 50

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC