M.D. Ercegovac and T. Lang, "On-Line Arithmetic: A Design Methodology and Applications in Digital Signal Processing," in VLSI Signal Processing III, vol. 3, 1988, pp. 252--263. Reprinted in E.E. Swartzlander, Computer Arithmetic, vol. 2, IEEE Computer Society Press Tutorial, Los Alamitos, CA, 1990, pp. 66--77.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in a digital communication receiver. On line arithmetic [5, 9, 11] has been developed and researched extensively over the past two decades. On line arithmetic has been shown to be very useful for many signal processing applications such as DCT, FFT, CORDIC, filtering and matrix based operations [3, 7]. In conventional arithmetic, all digits of the result must be computed before the next operation can be started. However, in on line arithmetic, the operands, as well as the results, flow through the computations in a digit by digit manner, starting from the most significant digit (MSDF) The ....

....us to stop computations as soon as the first non zero MSD (sign) has been calculated. This not only avoids the computations of the successive digits, but also eliminates the need for backconversion to a conventional number system. 2. Background on on line arithmetic On line arithmetic algorithms [5, 7] work in a digit serial manner, producing the result in a MSDF fashion. To generate the first output digit, digits of the input are required. Thereafter, with each digit of the input, a new digit of the result can be obtained. The on line delay is typically a small integer, e.g. 1 to 4. Since ....

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M. D. Ercegovac and T. Lang. On-line arithmetic: A design methodology and applications in digital signal processing. VLSI Signal Processing III, pages 252--263, November 1988. IEEE Press.

....to meet the mobile device constraints, but also has to accelerate detection to meet real time performance requirements. On line arithmetic [4] 5] 6] has been shown to be very useful for many signal processing applications such as DCT, FFT, CORDIC, filtering and matrix based operations [7], 8] In conventional arithmetic, all digits of the result must be computed before the next operation can be started. However, in on line arithmetic, the operands, as well as the results, flow through the computations in a digit by digit manner, starting from the most significant digit (MSDF) ....

....The detected bits are then sent to the decoder for retrieving the transmitted information. Each stage of the multiuser detector uses only adders because multiplication by single bits can be reduced to addition and subtraction. B. On line arithmetic background On line arithmetic algorithms [4] [7] work in a digit serial manner, producing the result in a MSDF fashion. To generate the first output digit, digits of the input are required. Thereafter, with each digit of the input, a new digit of the result can be obtained. The on line delay, is typically a small integer, e.g 1 to 4. ....

M. D. Ercegovac and T. Lang, "On-line arithmetic: A design methodology and applications in digital signal processing," VLSI Signal Processing III, pp. 252--263, November 1988, IEEE Press. 30

....to meet the mobile device constraints, but also has to accelerate detection to meet real time performance requirements. On line arithmetic [3] 4] 5] has been shown to be very useful for many signal processing applications such as DCT, FFT, CORDIC, filtering and matrix based operations [6], 7] In conMay 27, 2002 Rice University Technical Report ventional arithmetic, all digits of the result must be computed before the next operation can be started. However, in on line arithmetic, the operands, as well as the results, flow through the computations in a digit by digit manner, ....

....to be performed in case of soft decisions. Thus on line arithmetic applies across both schemes and the tradeoff is between increased throughput for detection and the desired error rate performance needed by the mobile receiver. B. On line arithmetic background On line arithmetic algorithms [3] [6] work in a digit serial manner, producing the result in a MSDF fashion. To generate the first output digit, digits of the input are required. Thereafter, with each digit of the input, a new digit of the result can be obtained. The on line delay, is typically a small integer, e.g 1 to 4. Since ....

M. D. Ercegovac and T. Lang, "On-line arithmetic: A design methodology and applications in digital signal processing," VLSI Signal Processing III, pp. 252--263, November 1988, IEEE Press.

....is made at the decoder. entire precision is kept to help make an improved hard decision with higher accuracy at the end of detection. On line arithmetic has been shown to be very useful for many signal processing applications such as DCT, FFT, CORDIC, filtering and matrix based operations [5, 6]. In conventional arithmetic, all digits of the result must be computed before the next operation can be started. However, in on line arithmetic, the operands, as well as the results, flow through the computations in a digit by digit manner, starting from the most significant digit (MSDF) On line ....

....representation is m = 4. We choose an 8 bit precision implementation (d = 8) as it is shown to be sufficient for most detection implementations [4] We assume that the on line implementation time t OL per digit takes approximately twice the time of conventional implementation t conv per bit [5]. Hence, t OL 2, as we choose the basic unit of conventional addition time, t conv = 1. The time taken for t stop depends on the magnitude and sign of the operands. The values of t stop now range between 0 t stop 4 2 = 8. We assume that, on an average, t stop = 2 for an 8 bit ....

M. D. Ercegovac and T. Lang, "On-line Arithmetic: A Design Methodology and Applications in Digital Signal Processing," VLSI Signal Processing III, pp. 252--263, November 1988, IEEE Press.

....receiver. The detector produces either singlebit precision outputs (hard decisions) of the detected bits or higher precision outputs (soft decisions) The final decision on the transmitted information is made at the decoder. such as DCT, FFT, CORDIC, filtering and matrix based operations [5, 6]. In conventional arithmetic, all digits of the result must be computed before the next operation can be started. However, in on line arithmetic, the operands, as well as the results, flow through the computations in a digit by digit manner, starting from the most significant digit (MSDF) On line ....

....and hence, the on line algorithms can increase the overall speed by overlapping computations with the conversion. Other signal processing applications involving sign based computations can also benefit from an on line approach. II. Background on on line arithmetic On line arithmetic algorithms [5, 7] work in a digit serial manner, producing the result in a MSDF fashion. To generate the first output digit, digits of the input are required. Thereafter, with each digit of the input, a new digit of the result can be obtained. The on line delay is typically a small integer, e.g 1 to 4. Since the ....

[Article contains additional citation context not shown here]

M. D. Ercegovac and T. Lang, "On-line Arithmetic: A Design Methodology and Applications in Digital Signal Processing," VLSI Signal Processing III, pp. 252--263, November 1988, IEEE Press.

....in a digital communication receiver. On line arithmetic [5, 9, 11] has been developed and researched extensively over the past two decades. On line arithmetic has been shown to be very useful for many signal processing applications such as DCT, FFT, CORDIC, filtering and matrix based operations [3, 7]. In conventional arithmetic, all digits of the result must be computed before the next operation can be started. However, in on line arithmetic, the operands, as well as the results, flow through the computations in a digit by digit manner, starting from the most significant digit (MSDF) The ....

....us to stop computations as soon as the first non zero MSD (sign) has been calculated. This not only avoids the computations of the successive digits, but also eliminates the need for backconversion to a conventional number system. 2. Background on on line arithmetic On line arithmetic algorithms [5, 7] work in a digit serial manner, producing the result in a MSDF fashion. To generate the first output digit, digits of the input are required. Thereafter, with each digit of the input, a new digit of the result can be obtained. The on line delay is typically a small integer, e.g. 1 to 4. Since ....

[Article contains additional citation context not shown here]

M. D. Ercegovac and T. Lang. On-line arithmetic: A design methodology and applications in digital signal processing. VLSI Signal Processing III, pages 252--263, November 1988. IEEE Press.

....Conventional communication systems with area and power constraints can be implemented with bit serial arithmetic systems [1] 2] In bit serial arithmetic, the arithmetic units are bitwide and the operations flow from least significant digit to the most significant digit. On line arithmetic [3] [4] works in a digit serial manner, producing the result in a Most Significant Digit First (MSDF) fashion. This is useful for many communication algorithms where only a few of the most significant digits are required, for example: detection [15] Hence, this leads to a high speed low area design ....

M. D. Ercegovac and T. Lang, "On-line arithmetic: A design methodology and applications in digital signal processing," VLSI Signal Processing III, pp. 252--263, November 1988, IEEE Press.

....on the algorithm and the throughput required by the application. PE s are build from a number of basic computational units (BCU s) registers, multiplexors and local control logic. BCU s are based on the bit serial least significant digit first [30] or most significant digit first On Line [31] computational style due to the good time area trade offs and suitableness for DSP algorithms [32] Besides local control logic also global control logic is used. These control signals may either be pipelined through the array or broadcasted. Typically, time critical control signals with little ....

M. D. Ercegovac and T. Lang, "On-Line Arithmetic: A Design Methodology and Applications in Digital Signal Processing," in VLSI Signal Processing III, pp. 252--263, 1988.

....to as ffi bit serial computations instead of bit serial or digit serial. We adopt this notation in the remaining of the presentation. Thus far all the investigations in ffi bit serial architectures assumed logic implementation with technologies that directly implement Boolean gates [19] 20] [21], 22] 23] and no studies have been dedicated to such designs using threshold based neural networks. We assume LSB first operand reception and investigate ffi bit serial addition and multiplication in the context of feed forward neural networks. We are mainly concerned in establishing the limits ....

M.D. Ercegovac and T. Lang, On-Line Arithmetic: A Design Methodology and Applications, vol. VLSI Signal Processing, III, chapter 24, IEEE Press, Los Angeles, 1988.

....can thus be exploited while computation is still in progress. This allows dynamically pushing the computation precision to any extent as also a high degree of parallelism when many operators are pipelined. The interest of serial operators in signal processing applications has been widely published [4 9]. However, serial, least significant digit first operations are limited to addition and multiplication, whereas on line arithmetic allows the computation of the most common mathematical functions[1013 ] While several papers have been published on the test of serial least significant digit first ....

M.D. Ercegovac and T.Lang " On-line arithmetic : a design methodology and applications to signal processing," VLSI Signal Processing . Chapter 24, pp. 252-263 IEEE Press 1988.

....binary outputs. In turn, VPC for every binary function questions: At what precision does this instance need to be evaluated In general, VPC can be used in computations whose set of possible outcomes does not increase as the operand precision increases. VPC is similar to on line arithmetic [EL88] operands are processed bit serially from the most significant bit. As a composite operator, the metric is not evaluated as a sequence of atomic operations (e.g. multiplications, additions) Instead, we merge these operations and rewrite the algorithm in terms of a composite operator which ....

....Summary of previous implementations. Year First Author Precision Measure Operator Algorithm [Reference] bits) 1984 Tao [TAG84] 8 MSE parallel VQ 1986 Davidson [DG86] 12 MSE parallel VQ 1986 Nelson [NR86] 9 MSE serial VQ 1987 Abut [ATS87] 8 MSE parallel VQ 1987 Dionysian[DB87] 7 IP parallel VQ 1988 Davidson[DCG88] 12 IP parallel VQ 1989 Ramamoorthy [RPT89] 9 MSE serial VQ 1990 Fang [FCS90] 8 IP parallel TSVQ 1992 Dezhgosha [DJK92] 9 MAD parallel VQ 1993 Kolagotla [KYJ93] 8 IP parallel TSVQ on the application. Image pixels used in VQ compression are 8 bits. Depending on the ....

[Article contains additional citation context not shown here]

M. D. Ercegovac and T. Lang. On-line arithmetic: A design methodology and applications in digital signal processing. IEEE Workshop on VLSI Signal Processing, Vol. III:252--263, 1988.

....15 and conclusion. 2 On line algorithms for ax b (OMA) module We now discuss an on line algorithm for the multiply add operation y = ax b where a is in parallel and x and b in digit serial form. All inputs are fractions, i.e. 1=2 a; x; b 1. The recurrence equation is derived following [ 4 ]. At step j, the error between the actual and computed function values is bounded by jax[j] b[j] Gamma y[j]j r Gammaj where x[j] j ffi X i=0 x i r Gammai ; b[j] j ffi X i=0 b i r Gammai and y[j] j X i=0 y i r Gammai and x j ; b j 2 f Gammaae; aeg; ae r ....

....a simplified radix r on line adder to recode the output digit into a redundant set as discussed later. The overall timing relations during on line operation is shown bellow where y j = t j s j 1 : x j 1 x 0 x 1 x 2 x 3 x 4 x 5 x 6 b j 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 W [j] W [1] W [2] W [3] W [4] W [5] y j t 0 t 1 t 2 t 3 t 4 t 5 s 1 s 2 s 3 s 4 s 5 s 6 y j y 0 y 1 y 2 y 3 y 4 y 5 Another way of dealing with the over redundant output digits is to use it directly (without recoding) in forming the product a Theta x j . This may require an increase in reduction stages (increasing the ....

Ercegovac, M. D. and Lang T.; On-line Arithmetic: A design Methodology and Applications; IEEE Workshop on VLSI, 1988.

....parallel form. We then modify the E method into a fully on line version to be used with the VP method. 1. 1 On line arithmetic In on line computations, the operands, as well as the results, fl ow through arithmetic units in a digit by digit manner, starting with the most signifi cant digit [24, 12, 10, 13]. In order to generate the j th digit of the result, j ffi ) digits of the operands are required. The on line delay ffi is usually a small integer. The outputs are obtained digit by digit in a redundant form, and, if desired can be converted to parallel conventional form using the on the ....

M.D. Ercegovac and T. Lang. On- Line Arithmetic: A design methodology and applications. VLSI Signal Processing, III, IEEE Press 1988, pp. 252- 263.

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M.D. Ercegovac and T. Lang, "On-Line Arithmetic: A Design Methodology and Applications in Digital Signal Processing," in VLSI Signal Processing III, vol. 3, 1988, pp. 252--263. Reprinted in E.E. Swartzlander, Computer Arithmetic, vol. 2, IEEE Computer Society Press Tutorial, Los Alamitos, CA, 1990, pp. 66--77.

No context found.

M. D. Ercegovac and T. Lang, On-Line Arithmetic: A Design Methodology and Applications, vol. VLSI Signal Processing, III, ch. 24. New York: IEEE Press, 1988.

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Milos D. Ercegovac and Tomas Lang. On-line Arithmetic: A Design Methodology and Applications. 1988 IEEE Workshop on VLSI Signal Processing. Chapter in VLSI Signal processing III.

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Ercegovac88 Milos D. Ercegovac and Thomas Lang, "On-line Arithmetic: A Design Methodology and Applications in Digital Signal Processing. VLSI Signal Processing, III 1988.

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M.D. Ercegovac and T. Lang " On-line arithmetic : a design methodology and applications to signal processing," VLSI Signal Processing . Chapter 24, IEEE Press 1988.

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