V. K. R. Chiluvuri and I. Koren, "Layout-synthesis techniques for yield enhancement," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 178--187, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....work has been reported by [1] where a set of local rules have been proposed for contacts, metal and polysilicon layers for yield enhancement. However, the techniques involved are not general enough to be applied on the regular physical layout compaction. In the second method reported by [3], a heuristic algorithm increases the spacing of layout by changing the positions of only the objects off the critical path, while layout area is maintained at its minimum area. This heuristic however does not guarantee optimum yield. The method that considers tightly the fault probability is ....

V. K. R. Chiluvuri and I. Koren, Layout-synthesis techniques for yield enhancement ," IEEE Transactions on Semiconductors and manufacturing, vol. 8:2 pp. 178-187, May 1995.

....parameters determine the electrical and geometric constraints affecting the layout in the library, while layout architecture and performance requirements constrain the process variables. A variety of techniques have been developed to create optimized layout given a set of process parameters [1][2] and recently operations research techniques have been applied to optimizing processes and libraries together. 3] The optimization problem is often constrained by EDA trade offs faced during creation of the layout. The central trade off is the one between the level of automation and layout ....

V.K.R. Chiluvuri and I. Koren, "Layout-Synthesis Techniques For Yield Enhancement", IEEE Trans. on Semiconductor Manufacturing, v. 8:2, pp. 178187, May 1995

....solution at a reasonable point on the price performance curve, a total variability budget for the design must be distributed among such attributes. In very deep submicron technologies, attaining large process windows and uniform manufacturing while bounding variability is difficult [6] 27] 19] [3]. Hence, the manufacturing process has an increasingly constraining effect on physical layout design and verification. Many physical design and physical verification methods have been proposed to address such manufacturing issues as registration errors, photolithographic random effects, random ....

....layout design and verification. Many physical design and physical verification methods have been proposed to address such manufacturing issues as registration errors, photolithographic random effects, random spot defects, plasma and charging effects ( antenna effect ) etc. see such works as [18] [3] for reviews. The heightened interdependencies between design and manufacturing are due in part to a fundamental crossover point in the evolution of VLSI technology. This crossover point occurs when minimum feature dimensions and spacings decrease below the wavelength of the light source. Pattern ....

V. K. R. CHILUVURI AND I. KOREN, Layout-Synthesis Techniques for Yield Enhancement, IEEE Trans. Semiconductor Manufacturing, 8 (1995), pp. 178-- 187.

....for compaction strategies[9] 10] 11] 1.2 Previous Work There are several works which improve yield by spacing or compacting the layout. Chiluvuri and Koren introduced a compaction strategy which took a compacted channel and incrementally shifted wire locations to reduce layout defect sensitivity[3]. A strategy was also presented in this work which increased wire width to reduce the possibility of breaks. Another post route optimization strategy is called the LocDes spacer[4] This work introduced local design rules which were used to adjust elements in an IC layout wherever possible to ....

....number of signal layers. Two works are based on a a) Rubber band sketch b) Extended rubber band sketch Figure 1: RBS and geometric transformation c) Geometric transformation a) proposed RBU operation b) RBU result a c b a b c Figure 2: Rubber Band Updating Operation channel based layout [3][5] which is becoming less popular. Area based layouts are not exclusive to IC design but also applicable to various packaging technologies such as MCMs, and board layouts such as PCMCIA. Also, octilinear wiring is also becoming more popular as designers attempt to reduce wire length. In addition ....

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V. Chiluvuri, and I. Koren, "Layout-Synthesis Techniques for Yield Enhancement," IEEE Trans. on Semiconductor Manufacturing, vol. 8, no. 2, pp. 178187, May 1995.

....interconnect dimensions, contact shapes and parasitics, and interlayer dielectric thicknesses. A total variability budget for the design is distributed among such attributes. In very deep submicron technologies, large process windows and uniform manufacturing is difficult [5] 10] 22] 15] 17] [7], and the manufacturing process has an increasingly constraining effect on physical layout design and verification. Many physical design methods have been proposed to address various manufacturing issues such as registration errors, photolithographic random effects, etc. see such works as [16] ....

....[7] and the manufacturing process has an increasingly constraining effect on physical layout design and verification. Many physical design methods have been proposed to address various manufacturing issues such as registration errors, photolithographic random effects, etc. see such works as [16] [7] for reviews. In this paper, we address the problem of controlling the manufacturing variation that is due to chemical mechanical polishing (CMP) 15] 19] 29] CMP is the procedure by which wafers are polished Research at UCLA was supported by a grant from Cadence Design Systems, Inc. ....

V. K. R. Chiluvuri and I. Koren, Layout-Synthesis Techniques for Yield Enhancement, IEEE Trans. Semiconductor Manufacturing, 8 (1995), pp. 178--187.

....stretch various wire segments in order to maintain the original topology, resulting in longer nets with a large critical area for open circuit defects. Two approaches to yield enhanced compaction have been proposed. In one, local modi cations in the layout are made as a post compaction step [1, 5]. These modi cations reduce the sensitivity to defects by redistributing the spacing between elements and by increasing the width of several wires. Reductions in critical area of about 8 were reported [5] In the second approach (e.g. 2] the compaction algorithm is modi ed so that both the ....

....been proposed. In one, local modi cations in the layout are made as a post compaction step [1, 5] These modi cations reduce the sensitivity to defects by redistributing the spacing between elements and by increasing the width of several wires. Reductions in critical area of about 8 were reported [5]. In the second approach (e.g. 2] the compaction algorithm is modi ed so that both the critical area and the more traditional objectives of compaction are optimized. Since compaction is the last stage of the physical layout synthesis, the e ectiveness of the yield enhancement at this stage is ....

V.K.R. Chiluvuri and I. Koren, "Layout Synthesis Techniques for Yield Enhancement," IEEE Trans. on Semiconductor Manufacturing, vol. 8, Special Issue on Defect, Fault, and Yield Modeling, May 1995, pp. 178-187.

....on the results of testing the fabricated chips. Fault tolerance of the microcontroller can be achieved by the use of standard memory fault tolerance techniques like adding spare rows and columns[3] Related research in CAD for manufacturability is briefly outlined. Recently, Chiluvuri and Koren[5] have developed layout compaction and routing algorithms to maximize defect tolerance. At the RT level, Guerra et al. 2] have presented a technique for incorporating BISR to enhance the yield of VLSICs. They use redundant functional units to overcome permanent fabrication time faults. In the ....

V. Chiluvuri and I. Koren, "Layout synthesis techniques for yield enhancement", in IEEE Trans. on Semiconductor Manufacturing, pp. 178--187, May 1995.

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V. K. R. Chiluvuri and I. Koren, "Layout-synthesis techniques for yield enhancement," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 178--187, 1995.

No context found.

V. K. R. Chiluvuri and I. Koren. Layout-synthesis techniques for yield enhancement. IEEE Transactions on Semiconductor Manufacturing, 8(2):178--187, May 1995.

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V. K. R. Chiluvuri and I. Koren. Layout-synthesis techniques for yield enhancement. IEEE Transactions on Semiconductor Manufacturing, 8(2):178--187, May 1995.

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