Tse-Yu Yeh, Yale N. Patt, "A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History," 20th Intl. Symp. on Computer Architecture, pp. 257-266, May. 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....The first dynamic branch predictors [23] primarily relied on local history information to make their predictions. Since that time, conditional branch predictors have undergone steady improvements. These improvements fall into three basic categories. 1) adding global path and history information [19, 24, 27] (2) refining the ways that global and local history are combined [3, 15] 3) reducing table interference through more intelligent table indexing schemes [5, 10, 12, 16, 22] Virtually all the conditional branch predictors proposed to date use control flow information as basic inputs either in ....

....Future research will focus on further extending the amount and type of information embedded in the REP. Since the REP tags are computed in parallel with the array access, adding or modifying the information used in the prediction is easy. For instance, further research may find more local history [27] and path history [7, 19, 24] are helpful. The information used in the REP can even be adapted dynamically. Rather than a one size fits all approach, predictor parameters can be adjusted to suit the program being run. For instance, this study correlated on a single single branch difference ....

Tse-Yu Yeh, Yale N. Patt, "A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History," 20th Intl. Symp. on Computer Architecture, pp. 257-266, May. 1993.

....major categories of work that are concerned with reducing the adverse effects of control flow on processor performance. Work in the first category tackles the control flow problem by reducing the number of mispredictions. There are numerous studies on branch prediction, for example Yeh and Patt [23], McFarling [12] Sprangle [18] and Lee et al. [9] to name just a few. Multi block ahead prediction [16] and hierarchical prediction in Multiscalar [7, 14] has been proposed to predict across multiple basic blocks in one cycle. The second category of work, which is closer related to SEE, strives ....

Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. In 20th Intl. Symp. on Computer Architecture, pages 257--266, May 1993. 10

....ixx av L lcom l lcom av I idl i idl av P porky R richards r richards av T troff t troff av Figure 38. Overhead in cycles (relative to P96) for varying branch penalties 77 tional and indirect branches since the former can better be predicted with local history based two level predictors [135]. The BTB is used exclusively to predict indirect branches. Thus, D D D D D D D D D D D D D d d d d d d d d d d d d d E E E E E E E E E E E E E e e e e e e e e e e e e e X X X X X X X X X X X X X x x x x x x x x x x x x x L L L L L L L L L L L L L l l l l l l l l l l l l l I I I I I I I I I I I I ....

....90 100 Misprediction rate BTB BTB 2bc History Pattern (p targets) History Table Figure 50. Two level branch prediction Branch Address Key Predicted Target 97 For conditional branches, a branch history of length p consists of the taken not taken bits of the p most recently executed branches [135]. In contrast, most indirect branches are unconditional, and thus keeping a history of taken not taken bits would be ineffective. Instead, the history must consist of previous target addresses or bits thereof. Such a path based history could also be used to predict conditional branches, but since ....

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Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. Proceedings of ISCA'93.

....at a later point in time when the operands to the branch instruction are available. Let BrP red( 2 PC B be any branch prediction function (it is assumed that this function can be computed in O (1) time) BrP red can be any realistic branch prediction function such as those discussed in [13, 15, 21] or could be something unimplementable, such as an oracle. The timestamping rule for branches with prediction is: PC : if BrP red(PC) R arg1 hcondiR arg2 ) 4) then PC else max Rarg1 ; Rarg2 ; PC LatBr The latency LatBr includes the amount of time to perform the ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 257--266, 1993. 15

....that at least some of the instructions we speculatively execute will be useful. It is possible to use a combination of the two, fanning out part of the time and predicting the rest of the time. This paper presents results concerning three questions. First, recent work in branch prediction [8, 10, 18, 19] has shown how to use very large predictors to improve the performance of hardware predictors from around 92 success to around 98 . What effect does this have on instruction level parallelism Second, how useful is a fan out capability, both by itself and in combination with a predictor Third, ....

....but unfortunately increasing the size of the table does not help much; the success rate levels off at 92 or 93 regardless of the table size. 2 SPECULATIVE EXECUTION AND INSTRUCTION LEVEL PARALLELISM Recent studies have explored more sophisticated hardware prediction using branch histories [10, 18, 19]. These approaches maintain tables relating the recent history of the branch (or of branches in the program as a whole) to the likely next outcome of the branch. These approaches do quite poorly with small tables, but unlike the two bit counter schemes they can benefit from much larger ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. Twentieth Annual International Symposium on Computer Architecture,

....both branch prediction and cache implementation. Static branch prediction is used by the machines presented here. However, it is possible to improve branch prediction rates with more sophisticated hardware methods that record run time behavior of the programs [Los82] LS84] YP91] PSR92] YP92] [YP93] [YS94] YGS95] The effect of improved branch prediction accuracy on machine performance is the subject of the next section. 6.2 Cost of a Miss Predicted Branch This section investigates the performance costs of miss predicted branches. In a machine without speculative execution and a static ....

Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. In ISCA-93, pages 257--266. IEEE, 1993.

....during run time. The misprediction rate of semi static branch prediction strategies is about half that of the best static branch prediction strategies [BL93] The misprediction rate of the best dynamic branch prediction strategies is about half that of semistatic branch prediction strategies [YN93]. Compile time optimizations like code motion and speculative execution rely on an accurate branch prediction strategy. For many optimizations existing branch prediction strategies are not sufficient. So we looked for a method to improve the accuracy of compile time branch prediction. Our ....

....called it branch correlation. Later Yeh and Patt studied all nine combinations of one global history register, a history register for a set of branches and a history register for each branch with one global pattern table, a pattern table for a set of branches or a pattern table for each branch [YN93]. The best strategy, a history register for each branch and a pattern table for a set of branches, achieved an average misprediction rate of about 3 having an implementation cost of 128K bits. 3 Collecting Branch Correlation Information We are interested in a branch prediction strategy usable ....

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Tse-Yu Yeh and Yale N.Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International

....behind this approach is that sections of code deal with related information, so control flow points dependent on a particular condition are likely to be placed near control flow points for related conditions. Exploiting the correlation between these conditions may lead to more accurate prediction [104, 106]. An illustration of this approach is given in Figure 5.6. The figure shows N target patterns assembled in a pattern register. Each target pattern provides B bits, for a total of I bits, which are XORed with I bits from the supplied address (a technique introduced by McFarling with the gshare ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 257--266, San Diego, California, May 17--19, 1993. ACM SIGARCH and IEEE Computer Society TCCA. Computer Architecture News, 21(2), May 1993.

....major categories of work that are concerned with reducing the adverse effects of control flow on processor performance. Work in the first category tackles the control flow problem by reducing the number of mispredictions. There are numerous studies on branch prediction, for example Yeh and Patt [23], McFarling [12] Sprangle [18] and Lee et al. [9] to name just a few. Multi block ahead prediction [16] and hierarchical prediction in Multiscalar [7, 14] has been proposed to predict across multiple basic blocks in one cycle. The second category of work, which is closer related to SEE, strives ....

Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. In 20th Intl. Symp. on Computer Architecture, pages 257--266, May 1993.

....behind this approach is that sections of code deal with related information, so control flow points dependent on a particular condition are likely to be placed near control flow points for related conditions. Exploiting the correlation between these conditions may lead to more accurate prediction [104, 106]. An illustration of this approach is given in Figure 5.6. The figure shows N target patterns assembled in a pattern register. Each target pattern provides B bits, for a total of I bits, which are XORed with I bits from the supplied address (a technique introduced by McFarling with the gshare ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 257--266, San Diego, California, May 17--19, 1993. ACM SIGARCH and IEEE Computer Society TCCA. Computer Architecture News, 21(2), May 1993.

....is some expense in undoing speculative execution when the branch goes the other way, we might impose a threshold so that we don t move instructions across a branch that is executed only 51 of the time. Recent studies have explored more sophisticated hardware prediction using branch histories [PSR92, YP92, YP93]. These approaches maintain tables relating the recent history of the branch (or of branches in the program as a whole) to the likely next outcome of the branch. These approaches do quite poorly with small tables, but unlike the two bit counter schemes they can benefit from much larger predictors. ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. Twentieth Annual International Symposium on Computer Architecture, 257--266, May 1993.

....604 hasa 64 entry fully associative BTB that holds the target address of the most recently taken branches, and uses a separate 512 entry pattern history table (PHT) to predict the direction for conditional branches. There are several different PHT variations. Pan et al. 12] and Yeh and Patt [20, 22] investigated branch correlation or two level branch prediction mechanisms. Although there are a number of variants, these mechanisms generally combine the history of several recent branches to predict the outcome of a branch. The simplest example is the degeneratemethod of Pan et al. 12] When ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International Symposium on Computer Architecture, pages 257--266, San Diego, CA, May 1993. ACM.

....four or more instructions per cycle. As a result, such architectures are likely to execute branch instructions every two cycles or less and effective branch prediction on such architectures is extremely important. Many approaches have been taken to branch prediction, some of which involve hardware [5, 27] while others involve software [3, 6, 12] Software methods usually work in tandem with hardware methods. For example, some architectures have a likely bit that can be set by a compiler if a branch is determined to be likely taken by a compiler. Compilers typically rely on two general approaches ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International Symposium on Computer Architecture, pages 257--266, San Diego, CA, May 1993. ACM.

....superior to the other. 3.2 Two level prediction for indirect branch paths With BTBs, the table storing the predicted target is accessed using the current branch address as the index. In two level branch predictors, the index is a history pattern based on previously executed branches [YP91] [YP93]. The goal of two level branch prediction is to map branch execution patterns to branch targets, allowing the prediction to use past behavior for better prediction. Most of the variations in two level predictors come from different answers to two basic questions, which we treat in the following ....

....branches within the C benchmarks that correspond to virtual function calls. 6 3.2. 1 First level: what comprises the history pattern For conditional branches, a branch history of length p consists of the taken not taken bits of the p most recently executed branches of a particular category [YP93]. Categories can be defined in several ways, leading to different history patterns. One one end of the spectrum of choices, a global history (correlation branch prediction) uses a single history, and all branches are predicted using the outcome pattern of the p most recently executed branches. In ....

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Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. Proceedings of ISCA'93.

....and needs to be predicted, the PC address of the branch instruction goes to a Pattern Selector, which chooses one of the 2 n entries in the PHT. The contents of that entry go through an output function to produce a prediction of either 2 This term is from the taxonomy paper of Yeh and Patt [15], though other names also appear in the literature. Pattern History Table (2 entries) PC Output Function Prediction Outcome n Function State Next Selector Pattern n Figure 1: Generic Dynamic Branch Prediction 11 10 01 00 N N N N T T T T Figure 2: 2 Bit Branch Prediction State Machine ....

.... uncorrelated 2 bit counter scheme described earlier) to k = n (a degenerate case in which prediction is based solely on global branch history) Typically, an intermediate value yields the best overall accuracy. Many other designs have been proposed and studied. The SAs predictor of Yeh and Patt [15] uses more than one BHB in its Pattern Selector. The lower i bits of the branch address map into a Branch History Table containing 2 i k bit shift registers. The k bits fetched are concatenated with n Gamma k bits from the original branch address to select an entry from the PHT. Other variants ....

[Article contains additional citation context not shown here]

Tse-Yu Yeh and Yale N. Patt, "A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History," in Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, California, pp. 257--266, May 1993.

....flow; Yeh Patts design includes additional information indicating whether the break is a conditional branch, unconditional jump, indirect jump or a return instruction. Each BTB entry also contains a per basic block pattern history register, used to index into a 2 level branch history table [20, 22]. Architectures using BTB s can issue a large number of instructions per cycle because of accurate branch and fetch prediction. However, BTB s lead to a complex architecture. In this paper, we show how to achieve the same or better performance using simpler techniques. We do this by: ffl ....

....and 2 bit techniques that yield much better performance for programs with loops [10, 13, 17] The advantage of the pattern history tables is that they keep track of very little information per conditional branch site and are very effective in practice. More recently Pan et al. [14] and Yeh and Patt [20, 22] have proposed branch correlation or two level branch prediction mechanisms. Although there are a number of variants, these mechanisms generally combine the history of several recent branches to predict the outcome of an incipient branch. The simplest example is the so called degenerate method of ....

[Article contains additional citation context not shown here]

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International Symposium of Computer Architecture, pages 257--266, San Diego, CA, May 1993. ACM.

.... flow; Yeh Patts design includes additional information indicating whether the break is a conditional branch, unconditional jump, indirect jump or a return instruction and each BTB entry contains a per basic block prediction history register, used to index into a 2 level branch history table [15, 17]. Architectures using BTB s can issue a large number of instructions per cycle because of accurate branch and fetch prediction. However, BTB s lead to a complex architecture. In this paper, we show how to achieve the same or better performance using simpler techniques. We do this using: ffl A ....

....and 2 bit techniques that yield much better performance for programs with loops [13, 8, 10] The advantage of these bit table techniques is that they keep track of very little information per conditional branch site and are very effective in practice. More recently Pan et al. [11] and Yeh and Patt [15, 17] have proposed branch correlation or two level branch prediction mechanisms. Although there are a number of variants, these mechanisms generally combine the history of several recent branches to predict the outcome of an incipient branch. In this paper, we are primarily concerned with 2 level ....

[Article contains additional citation context not shown here]

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International Symposium of Computer Architecture, pages 257--266, San Diego, CA, May 1993. ACM.

....we want to remove, branch misfetch and mispredict penalties. A branch target buffer can be used to reduce the misfetch penalty and can be used as a simple branch prediction mechanism. Other branch prediction methods can reduce mispredict penalties, but not misfetch penalties. Many architectures [33, 40, 42] combine branch target buffers and other branch prediction mechanisms to reduce both misfetch and mispredict penalties. 2.1 Branch Target Buffers Misfetch penalties can be reduced in a number of ways, such as using branch delay slots [24] a table of cache indices for fetch prediction [8] or ....

....the branch direction, even if that information was recorded for one of the other branches. The advantage of the pattern history tables is that they keep track of very little information per conditional branch site and are very effective in practice. More recently Pan et al. [28] and Yeh and Patt [40, 42] have proposed branch correlation or two level branch prediction mechanisms. Although there are a number of variants, these mechanisms generally combine the history of several recent branches to predict the outcome of an incipient branch. The simplest example is the so called degenerate method ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International Symposium of Computer Architecture, pages 257--266, San Diego, CA, May 1993. ACM.

....an indirect function call can have a large number of potential targets. We have measured programs with 191 different subroutines called from a single indirect function call. This makes branches easier to predict. Some dynamic branch prediction mechanisms achieve 95 Gamma97 prediction accuracy [21, 27, 29]. This level of accuracy is needed for super scalar processors issuing several instructions per cycle [28] The most relevant prior work was on predicting the destination of indirect function calls with hardware conducted by David Wall [26] while examining limits to instruction level parallelism. ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In 20th Annual International Symposium of Computer Architecture, pages 257--266, San Diego, CA, May 1993. ACM.

....3.2 Processor Model The processor model is a superscalar processor that uses the PowerPC instruction set and supports register renaming, speculative execution, out of order execution and true out of order retirement graduation commitment 1 . The branch prediction algorithm is two level adaptive [23] with a single global branch history register. We modeled two CPU configurations, the simple and advanced models, whose characteristics are presented in Table 2. The parameters for the simple model were chosen to be roughly comparable to currently available processors, while the advanced ....

Tse-Yu Yeh and Yale N. Patt. "A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History," In 20th International Symposium on Computer Architecture (ISCA 1993), pages 257--266, San Diego, CA, 1993.

....is predicted to occur. The DBTB entry also contains branch prediction information about all the potential branches in the referenced line. It may contain no information at all, a one bit prediction, a two bit saturating prediction, or advanced prediction methods such as two level branch history [10]. 5 Expected Instruction Fetch The total expected instructions fetched per cycle for simple, extended, and selfaligned fetching are F simple (n; b) n 1 b(n Gamma 1) 3) PC tag exit position branch prediction info BTB1 BTB2 exit position branch prediction info predicted PC1 PC1 ....

Tse-Yu Yeh and Yale N. Patt.: A comparison of dynamic branch predictors that use two levels of branch history. Proceedings of the 20th International Symposium on Computer Architecture (1993) 257--266.

....requires prior specific permission and or a fee. of the classes conditional direct, unconditional direct, and unconditional indirect occur with significant frequency. In the past, branch prediction research has focused on accurately predicting conditional and unconditional direct branches [11, 7, 15, 6, 2, 8]. To predict such branches, the prediction mechanism predicts the branch direction (for unconditional branches, this part is trivial) and then generates the target associated with that direction. To generate target addresses, a branch target buffer (BTB) is used. The BTB stores the fall through ....

Tse-Yu Yeh and Yale N. Patt. A comparison of dynamic branch predictors that use two levels of branch history. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 257--266, 1993.

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Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. Proceedings of ISCA'93.

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Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. Proceedings of ISCA'93.

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Tse-Yu Yeh and Yale N. Patt. A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History. Proceedings of ISCA'93.

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