C. Young, N. Gloy and M. Smith, "A Comparative Analysis of schemes for Correlated branch Prediction, " Proc. 22nd Annual Intl. Symp. on Computer Architecture, June, 1995. 208 Informatica 29 (2005) 199--207 W. Lin et al.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....benchmarks) is dangerous, but the speed di#erence between interpreters and native code compilers appears to be less than many people imagine. 8. RELATED WORK The accuracy of static conditional branch predictors has been improved with software methods: branch alignment [3] and code replication [12, 18, 17]. The present paper looks at using software methods to improve the accuracy of the BTB, a simple dynamic indirect branch predictor. Our code replication di#ers from replication for conditional branch prediction in all aspects: our work addresses a dynamic indirect branch predictor (the BTB) ....

C. Young, N. Gloy, and M. D. Smith. A comparative analysis of schemes for correlated branch prediction. In 22 nd Annual International Symposium on Computer Architecture, pages 276--286, 1995.

....is critically dependent on being able to accurately predict the control (branch) flow in the program, so that we can execute more useful instructions and avoid stalling squashing the pipeline. Branch predictors for control flow prediction have been studied extensively with different programs [29][31][23] 15] and also with OS effects [8] The OS affects control flow predictability by introducing the additional user OS branch aliasing in branch predictor tables. The negative impact of kernel branches on branch prediction has been reported in [8] We also find that kernel code nearly doubles the ....

C. Young, C. Gloy and M. D. Smith, A Comparative Analysis of Schemes for Correlated Branch Prediction, In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 276-286, 1995.

....aggressive schemes exposes both types of history, so we would expect alloying to remain superior. Yet other work has focused on characterizing why mispredictions happen in two level predictors, but these continue to focus on PHT interference. Talcott et al. 38] Sprangle et al. 36] Young et al. [42], and Chang et al. 2] characterized PHT interference and showed that while significant amounts of both constructive and destructive interference occur, the destructive interference consistently dominates. Evers et al. 6] and Juan et al. 19] discussed the importance of training time. Evers et ....

C. Young, N. Gloy, and M. D. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 276--86, June 1995. 34

....is critically dependent on being able to accurately predict the control (branch) flow in the program, so that we can execute more useful instructions and avoid stalling squashing the pipeline. Branch predictors for control flow prediction have been studied extensively with different programs [Yeh91, Young95, Sech96 and Mich97] and also with OS effects [Gloy96] The OS affects control flow predictability by introducing the additional user OS branch aliasing in branch predictor tables. The negative impact of kernel branches on branch prediction has been reported in [Gloy96] We also find that user OS execution can ....

C. Young, C. Gloy and M. D. Smith, A Comparative Analysis of Schemes for Correlated Branch Prediction, In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 276286, 1995

....prediction schemes, a conceptual view of a branch prediction scheme is introduced. This conceptual view allows us to compare various branch prediction schemes. It also enables us to focus and improve each component by clearly defining its function. This conceptual model elaborates on the one in [Young95]. Our model extends it to accommodate most popular branch prediction schemes. static information m Surce achine code ) program semantics algorithmic information code restructuring run time information InfQrmatlon: branch address opcode outcome target address hint bit statistics from ....

Young, C., Gloy, N. and Smith, M. A comparative analysis of schemes for correlated branch prediction. Proceedings of the 22nd International Symposium on Computer Architecture, 276-286, June 1995.

....bits to record the information on a single branch. Although the length of branch history which can be represented at the same hardware cost is shorter than in pattern based predictors, the path based predictor is slightly better than pattern based predictor in exploiting branch correlation [9]. Also it has an advantage of having a shorter training time for the same prediction accuracy. In all the above branch predictors and their variants, the branch history length is xed as a constant. Since branch history represents the interdependence between branch instructions executed ....

....history length exceeds a certain point for every SPECint95 benchmark program. This behavior is quite normal: since not all of the outcomes in the past branch history contains information relevant with the current branch, an unnecessarily long branch history would only incur more interference [9] and longer training time without yielding any bene cial e ect on prediction accuracy. Evers et al. 3] demonstrate that the outcomes of only a small number of previous branches are needed to make an accurate prediction. Furthermore, they show that the most 2 correlated branches are close together ....

C. Young, N. Gloy, and M. Smith. A comparative analysis of schemes for correlated branch prediction. In The 22nd Annual International Symposium on Computer Architecture (ISCA), pages 276-286, June 1995.

....Branch Elimination (ICBE) has a number of benefits, including # enhancing instruction scheduling and software pipelining, # improving speculative execution and hardware branch prediction, and # optimizing C Java virtual functions. Recent research in branch prediction [Kra94, SLM96, YGS95] profiling [BL96b] and the elimination of conditional branches [MW95b] has reported the existence of significant amounts of correlation among conditional branches, presenting opportunities for optimizations. Previous work on conditional branch elimination through static correlation [MW95b] ....

....cycle [Joh91] Our experiments have shown that between 3 and 18 of executed conditionals can be eliminated by ICBE, reducing branch density. A mispredicted branch stalls the processor for many cycles and pollutes the instruction cache. Research in correlation based hardware branch prediction [YGS95] shows that unpredictable branches exhibit correlation with earlier branches. Some unpredictable branches can arguably be eliminated by ICBE. Consider, for example, a procedure that removes an element from a linked list. When the average list length is low, the conditional that tests for an empty ....

Cliff Young, Nicolas Gloy, and Michael D. Smith. A comparative analysis of schemes for correlated branch prediction. In Intl. Symposium on Computer Architecture, Italy, 1995.

....bottlenecks and are relatively well researched topics. The design of instruction caches has been studied in great detail in order to lessen the impact of instruction cache misses on fetch bandwidth [31] 36] Likewise, there have been many studies done to improve branch prediction accuracy [16] [25]. To date, the techniques developed to reduce instruction cache misses and increase branch prediction accuracy have been very successful in improving fetch bandwidth. However, as the issue rates for superscalar processors increase beyond four, other additional factors become increasingly ....

....very admirable, there is still a great deal of room for improvement. Multiple branch prediction performance is becoming an important research area. The performance of the trace cache will undoubtedly increase as techniques to enhance multiple branch predictor performance continue to be developed [25] [27] Finally, the simulation results point out the important fact that size does matter. By increasing the trace cache from the original 4Kbyte size to a 64Kbyte configuration, there is an average fetch IPC improvement of 15.2 for integer benchmarks, and 5.8 improvement for floating point ....

C. Young, N. Gloy, and M. Smith, "A Comparative Analysis of Schemes for Correlated Branch Prediction," Proceedings from the International Symposium of Computer Architecture, June 1995

....[24,11,23] The transformations shown should increase the potential for exploiting these techniques. It should be noted that the SPARC processor that we considered, includes a fairly simple branch prediction scheme (2 bit prediction scheme) and that 2 level branch history based prediction schemes [21,29] could possibly also speed up the execution of the program by better predicting the outcome of the original branches. We proposed a static technique that transforms a sequence of control flow instructions into one parallel branch so that only one branch misprediction can take place and as such ....

C. Young, N. Gloy, and M.D. Smith. A comparative analysis of schemes for correlated branch prediction. In The 22nd Annual International Symposium on Computer Architecture, pages 276--286. ACM SIGARCH and IEEE Computer Society TCCA, ACM press, June 1995.

....that different history lengths for 2 level predictors performed better for different classes of branches. Although the design space for branch predictors grew tremendously, an understanding of how and why these predictors worked did not. More recently, however, a number of papers, such as [23], 12] 6] 16] and [4] have provided insights into mechanisms for creating more accurate branch predictors. Our goal is to continue this process towards a deeper understanding about the nature of branch behavior and branch predictor performance. In this paper, we introduce a new metric for ....

C. Young, N. Gloy, and M. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings 22nd Annual Intl. Symposium on Computer Architecture, pages 276--286, Santa Magherita Ligure, Italy, June 1995.

....instructions in length. Link Slices into Binary For each benchmark, the instructions from each p slice are appended to the program binary in a special program text segment. Steps can be taken to minimize potential instruction cache interference between the speculative thread and the main thread [24]. However, for this study we found instruction fetch for the p slices did not introduce any noticeable increase in I cache misses for the non speculative thread. 5.2. An Example MCF Figure 4 illustrates the source code for a key loop from the mcf benchmark. The loop contains three delinquent ....

C. Young, N. Gloy, and M. D. Smith. A comparative analysis of schemes for correlated branch prediction. In 22nd Annual International Symposium on Computer Architecture, pages 276--286, May 1995.

....each time the branch executes to produce a direction prediction [23, 26] But the size of these dynamic tables is limited, and sometimes two different branches end up sharing the same PHT entry. This is called prediction table interference, and is the main cause for decreased prediction accuracy [28]. Dynamic prediction tables can be organized in a clever way to reduce prediction table interference, leading to the recently proposed dealiased schemes [10, 12, 24] In this work we examine the effect on branch prediction accuracy of the code reordering optimizations which target the ....

....have been a misprediction, we talk about positive interference; if the conflict causes a misprediction when the old counter was correct, we talk about negative interference. Negative interference happens more often than positive interference, and is the main cause of decreased prediction accuracy [28, 20]. Dealiased branch predictors reduce negative PHT interference by changing the way they store data in the predic Branch address Global branch history Xor Pattern History Table (a) Gshare predictor (global history) Branch address Level 2 table Level 1 table (b) PAg predictor (private ....

C. Young, N. Gloy, and M. D. Smith. A comparative analysis of schemes for correlated branch prediction. Proceedings of the 22th Annual Intl. Symposium on Computer Architecture, June 1995.

....detect edge correlations at compile time. Instead, DDFA tries to eliminate paths at runtime, by using runtime control flow information. It should be possible to combine both techniques we have not yet investigated this angle. There has been considerable research recently in branch prediction [15, 22] and profiling [3] These techniques generally give probabilistic information about control flow directions. DDFA could use such information to guide its caching policies. The technique of deferring collection of dataflow information until runtime was used in a limited form (only procedure return ....

C. Young, N. Gloy, and M. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings of the 22nd ISCA, June 1995.

....investigated in the past few years, with each offering certain distinctive features. Most of them, however, share a common characteristic: they rely on a collection of 1 or 2 bit counters held in a predictor table. Each entry in the table records the recent outcomes of a given branch substream [21], and is used to predict the direction of future branches in that substream. A branch substream might be defined by some bits of the branch address, by a bit pattern representing previous branch directions (known as a branch history) by some combination of branch address and branch history, or by ....

....do not permit this. Chip die area budgets and access time constraints limit predictor table size, and most tables proposed in the literature are further constrained in that they are direct mapped and without tags. Fixed sized predictor tables lead to a phenomenon known as aliasing or interference [21, 16], in which multiple (address, history) pairs share the same entry in the predictor table, causing the predictions for two or more branch substreams to intermingle. Aliasing has been classified as either destructive (i.e. a misprediction occurs due to sharing of a predictor table entry) harmless ....

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C. Young, N. Gloy, and M.D. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.

....branches. Many proposals for dynamic branch prediction exist, with each offering certain distinctive features, but most share a common characteristic: they rely on a collection of 1 or 2 bit counters held in a predictor table. Each entry records the recent outcomes of a given branch substream [13], and is used to predict the direction of future occurrences of that substream. A branch substream might be defined by certain bits of a branch address, by a bit pattern representing previous branch directions (the branch history) or by some combination of branch address and branch history [9, ....

....[13] and is used to predict the direction of future occurrences of that substream. A branch substream might be defined by certain bits of a branch address, by a bit pattern representing previous branch directions (the branch history) or by some combination of branch address and branch history [9, 12, 13, 6, 5, 4]. Ideally, we would like to have a predictor table with infinite capacity so that every unique branch substream defined by an (address, history) pair will have a dedicated predictor. Real world constraints, of course, do not permit this; limited chip die area and access time constraints limit ....

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C. Young, N. Gloy, and M.D. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995. Irisa

....greatest benefit. The last two approaches identify dynamic occurrences of indirect branches using path history. By recording path history within a global history register, they are using a form of branch correlation. Branch correlation was first proposed for conditional branch prediction [17] [18]. Path based branch correlation has also been examined [19] Our attempt is different from all of the above techniques in that we use compile or run time information (i.e. profile data) to classify branches into several groups (or branch classes) All branches within a class exhibit a similar ....

C. Young, N. Gloy, and M.D. Smith. A Comparative Analysis of Schemes for Correlated Branch Prediction. In Proceedings of the International Symposium on Computer Architecture, pages 276--286, June 1995.

....They apparently use shorter inputs and do no warmup, a procedure which penalizes the dynamic selector. 6. Related Work A great deal of literature focuses on characterizing why mispredictions happen in two level predictors. Most, however, focus on PHT interference. For example, Young et al. [23] characterized PHT interference, and showed that while both significant amounts of both constructive and destructive interference occur, the destructive interference consistently dominates. Lee et al. 9] observed that conflicting substreams may be strongly biased, just in opposite directions, and ....

C. Young, N. Gloy, and M. D. Smith. A comparative analysis of schemes for correlated branch prediction. In Proc. ISCA22, pp. 276--86, June 1995. 8

....penalties and low cache miss penalties. Finally, we find that the application of profile driven code layout and branch alignment techniques (without SCBP) can improve the performance of the dynamic correlated branch prediction techniques. 1 Introduction Recent work in branch prediction [3, 18, 25, 30, 31, 32, 33] has led to the development of both hardware and software schemes that achieve high prediction accuracy by exploiting branch correlation. The motivation for this work stems from the fact that the performance of superscalar and deeply pipelined processors can benefit significantly from a small ....

....from a small improvement (a couple of percent points) in prediction accuracy. As with any technique however, there is a point of diminishing returns where the incremental costs of the technique begin to outweigh the further improvements. In static correlated branch prediction (SCBP) techniques [33], the cost of better prediction accuracy is code expansion, and thus, the point of diminishing returns is defined primarily by the relationship between the changes in the average access time of the instruction memory subsystem and the cycle count changes enabled by the improvements in prediction ....

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C. Young, N. Gloy, and M. Smith, "A Comparative Analysis of Schemes for Correlated Branch Prediction," Proc. 22nd Annual Intl. Symp. on Computer Architecture, June1995.

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C. Young, N. Gloy and M. Smith, "A Comparative Analysis of schemes for Correlated branch Prediction, " Proc. 22nd Annual Intl. Symp. on Computer Architecture, June, 1995. 208 Informatica 29 (2005) 199--207 W. Lin et al.

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C. Young, N. Gloy and M. Smith, "A Comparative Analysis of schemes for Correlated branch Prediction, " Proc. 22nd Annual Intl. Symp. on Computer Architecture, June, 1995.

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C. Young, N. Gloy and M. Smith, "A Comparative Analysis of schemes for Correlated branch Prediction, " Proc. 22nd Annual Intl. Symp. on Computer Architecture, June, 1995. 208 Informatica 29 (2005) 199--207 W. Lin et al.

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C. Young, N. Gloy and M. Smith, "A Comparative Analysis of schemes for Correlated branch Prediction, " Proc. 22nd Annual Intl. Symp. on Computer Architecture, June, 1995.

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Cliff Young, Nicolas Gloy, and Michael D. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.

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C. Young, N. Gloy, and M.D. Smith. A comparative analysis of schemes for correlated branch prediction. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.

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C. Young, N. Gloy, and M. D. Smith. A comparative analysis of schemes for correlated branch prediction. In 22nd International Symposium on Computer Architecture, pages 276--286, June 1995.

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