Katz, R. H., Eggers, S. J., Gibson, G. A., Hansen, P. M., Hill, M. D., Pendleton, J. M., Ritchie, S. A., Taylor, G. S., Wood, D. A. and Patterson, D. A. Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses. Computer Science Division, EECS, University of California, Berkeley, UCB/CSD 85/221, January 1985. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Cache Coherence Protocols for Large-Scale Multiprocessors - Chaiken (1990) (2 citations) (Correct)
....the system. Protocols that take advantage of this technique of covert observation are called snoopy cache coherence protocols, because each processor node snoops on the bus transactions of the other nodes. Snoopy protocols have been extensively studied, and have been implemented in several systems [20, 22, 26, 27]. Unfortunately, the protocols used in small multiprocessing systems do not scale up to systems with large numbers of processors, due to physical constraints on the processor interconnect structure. Specifically, a bus simply does not have the bandwidth to support a large number of high speed ....
R. H. Katz et al. Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses. Computer Science Division 85-221, University of California, Berkeley, January 1985.
Profile-Driven Compilation - Alan Dain Samples (1991) (4 citations) (Correct)
No context found.
Katz, R. H., Eggers, S. J., Gibson, G. A., Hansen, P. M., Hill, M. D., Pendleton, J. M., Ritchie, S. A., Taylor, G. S., Wood, D. A. and Patterson, D. A. Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses. Computer Science Division, EECS, University of California, Berkeley, UCB/CSD 85/221, January 1985.
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