R. Bianchini and T. J. LeBlanc. Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? In Proceedings of the 1994 International Conference on Parallel Processing, St. Charles, IL, August 1994. Expanded version available as TR 486, Computer Science Department, University of Rochester, January 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....at either 64 or 128byte lines. We believe that the degradation seen at larger sizes is due to a lack of bandwidth in our system. We note that the performance improvements seen by increasing the line size are progressively smaller for each increase. This is in agreement with the results in [11]. The exception to the above observations is mp3d under software coherence, where increases in line size hurt performance. The reason for this anomalous behavior is the interaction between cache accesses and remote references (uncached accesses) Longer cache lines have higher memory occupancy and ....

R. Bianchini and T. J. LeBlanc. Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? In Proceedings of the 1994 International Conference on Parallel Processing, St. Charles, IL, August 1994. Expanded version available as TR 486, Computer Science Department, University of Rochester, January 1994.

....from increases in cache line size and memory startup latency (as measured in processor cycles) longer lines increase the potential for false sharing, and increased memory startup costs increase the cost of servicing read misses. The trend toward increasing block sizes is unlikely to go on forever [2], and future improvements in compiler technology should serve to reduce the amount of false sharing seen for any particular block size. The parameters of the hypothetical machine seem plausible for the near term future, however, and suggest that lazy protocols will become increasingly important. ....

R. Bianchini and T. J. LeBlanc. Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? In Proceedings of the 1994 International Conference on Parallel Processing, St. Charles, IL, August 1994. Expanded version available as TR 486, Computer Science Department, University of Rochester, January 1994.

....(e.g. Dubnicki, 1993; Lee et al. 1987] have explored the relationship between block size and network bandwidth, but these studies either ignore one or more important factors (such as finite sized caches, or network contention) or assume a different architecture. We addressed these concerns in [Bianchini and LeBlanc, 1994], where we studied the relationship between cache block size and application performance as a function of remote access bandwidth and latency. 2.2 Sequential Prefetching Even when large cache blocks reduce the miss rate, the higher miss penalty may actually hurt overall performance. One way to ....

....0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10 Load Size TGauss Low Med High Inf Figure 12: MAST of TGauss under sequential prefetching. blocks reduce the miss rate by only a marginal amount. Furthermore, improvements in locality of reference may not translate to effective increases in the block size. See [Bianchini and LeBlanc, 1994] for a complete and detailed analysis of the effect of block size on the miss rate and application performance. 4.2 Sequential Prefetching In the previous section we saw that increasing the block size can drive up the miss rate or dramatically increase the miss penalty, which precludes the use of ....

R. Bianchini and T. J. LeBlanc, "Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors?," In Proceedings of the 1994 International Conference on Parallel Processing, August 1994, Extended version published as TR 486, Department of Computer Science, University of Rochester.

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