M. Weiss and G. Fettweis, "Dynamic codewidth reduction for vliw instruction set architectures in digital signal processors," in Proceedings of the 3rd. Int. Workshop in signal and Image Processing IWSIP'96, January 1996, pp. 571--520. Home/Search Document Details and Download
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Optimized Address Assignment for DSPs with SIMD.. - Lorenz, Kottmann.. (2001) (3 citations) (Correct)
....control, and the address generation unit. Unfortunately, the use of VLIW instruction set architectures leads to a code size overhead because sub instructions for idle units are also stored in the instruction memory. In order to reduce the code size overhead a Tagged VLIW (TVLIW) method is used [7]. The idea is that the next VLIW is assembled by an instruction decoder (fig. 2) for one or more TVLIW s which contain only functional unit instruction words (FIWs) for two function units (FUs) The number of required FIWs for assembling the next VLIW is indicated by the IWC (instruction word ....
M. H. Weiss and G. P. Fettweis. Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors. In 3rd International Workshop on Image and Signal Processing, pages 517--520. IEEE, 1996.
A HW/SW Design Methodology for Embedded SIMD Vector.. - Robelly, Cichon.. (2005) Self-citation (Fettweis) (Correct)
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M. Weiss and G. Fettweis, "Dynamic codewidth reduction for vliw instruction set architectures in digital signal processors," in Proceedings of the 3rd. Int. Workshop in signal and Image Processing IWSIP'96, January 1996, pp. 571--520.
Synchronous Transfer Architecture (STA) - Cichon, Robelly, Seidel, Matus.. (2004) Self-citation (Fettweis) (Correct)
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M. Wei and G. P. Fettweis. Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors. In 3rd. Int. Workshop in Signal and Image Processing (IWSIP `96), pages 517--520, Jan. 1996.
Compiler Scheduling for STA-Processors - Cichon, Robelly, Seidel, Bronzel, .. (2004) Self-citation (Fettweis) (Correct)
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M. Wei and G. P. Fettweis. Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors. In 3rd. Int. Workshop in Signal and Image Processing (IWSIP `96), pages 517--520, Jan. 1996.
Synchronous Transfer Architecture (STA) - Cichon, Robelly, Seidel, Matus.. (2004) Self-citation (Fettweis) (Correct)
No context found.
M. Wei and G. P. Fettweis. Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors. In 3rd. Int. Workshop in Signal and Image Processing (IWSIP `96), pages 517--520, Jan. 1996.
DSP Implementation Issues for UMTS-Channel Coding - Walther, Fettweis (2000) Self-citation (Fettweis) (Correct)
....each slice contains the corresponding part of a register file with special interconnections between the slices. The number of slices and their interior is defined by the target application. The di#erent parts of the machine are controlled via a modified VLIW instruction set architecture, TVLIW [4]: VLIW in order to provide parallelism, the modification increases code density and thus avoids code size explosion. The following example algorithm shows the applicability of the architecture. 3. UMTS CHANNEL CODING The coding scheme is two fold and incorporates a convolutional encoder for ....
M. Weiss and G. Fettweis, "Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors," in Proc. IWISP'96, 1996, pp. 517--520.
Applications for the Highly Parallel Mobile.. - Hosemann, Fettweis, .. (2002) Self-citation (Fettweis) (Correct)
....ISA [8] That is, the program memory consists of 32 bit T VLIW instructions which are extended to 80 bit VLIW instructions at the first decode stage by using a differential encoding for consecutive instructions. Thus, a higher code density than with conventional VLIW instructions can be achieved [9]. The single instruction multiple data (SIMD) paradigm is used for controlling all slices of the DSP core. Hence, all data path units perform the same operation. This keeps control efforts low while greatly boosting computational power. The SIMD paradigm is not only applied to control the ....
M. Weiss and G. P. Fettweis. Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors. In Proceedings of IWISP, 1996.
A Platform-Based Highly Parallel Digital Signal Processor - Richter, Drescher.. (2001) Self-citation (Weiss Fettweis) (Correct)
....for one clock cycle and each FU works on a separate instruction word. This principle, known as Very Long Instruction Word (VLIW) is disadvantageous in terms of code density. We therefore modified it to the Tagged Instruction Set Computing (TISC) previously referred to as TaggedVLIW (TVLIW) [5]. With this approach 32 bit wide instruction words in program memory contain only instructions for few FUs and are expanded by hardware to full VLIW width. To avoid penalty cycles for creating full VLIWs from TVLIWs a VLIW buffer is implemented. This software controlled buffer enables exploitation ....
Matthias Weiss and Gerhard Fettweis, "Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors", in Proc. of IWISP, pp. 517--520, 1996.
A Structural Approach For Designing Performance Enhanced .. - Weiss, Walther, Fettweis Self-citation (Weiss Fettweis) (Correct)
....used in the algorithm [5] Implementing a 31 by 16 MAC functionality can save approximately 6 of the MIPS and can be folded into a existing MAC unit to save cost. Implementing a dualMAC reduces the MIPS count significantly by 30 . Since dual MAC solutions already exist, e.g. by [7] or by [6], Algorithm appr. MIPS Requirement 1 Mac Arch. 4 MAC Arch. Lattice FIR 0.27 0.054 Lattice IIR 0.16 0.081 Cross Correlation 0.72 0.222 FIR 0.13 0.046 Remainder 0.52 0.44 Table 1: Major Algorithms in GSM Fullrate we took a step beyond by implementing a quadrupleMAC which can save 47 of the MIPS ....
....a pipelined data memory and a pipelined instruction decoder, resulting in a instruction pipeline of variable length. 3. STRUCTURAL APPROACH FOR ISA DESIGN Controlling the pipeline mainly incorporates resolving hazards. In a data stationary CISC ISA pipeline hazards must be resolved by hardware [6]. Thus, if the instruction set is modified, both the instruction decoder and the hazard resolving hardware must be changed. To allow the programer or compiler to control the pipeline, time stationary ISAs are applied as in Lucent s DSP1618. Fig. 1. MIPS reduction by different datapath add ons 0 ....
[Article contains additional citation context not shown here]
M. Weiss and G. Fettweis, "Dynamic Codewidth Reduction for VLIW Instruction Set Architectures in Digital Signal Processors", 3rd International Workshop on Image and Signal Processing, 1996, pp. 517-520
A Cluster Architecture for Embedded Perception - Mathew, Davis, Parker (Correct)
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Weiss, M., and Fettweis, G. Dynamic codewidth reduction for vliw instruction set architectures in digital signal processors, 1996.
The Perception Processor - Binu Mathew The (2004) (Correct)
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WEISS, M., AND FETTWEIS, G. Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors, 1996.
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