P. R. Nuth, The Named-State Register File. PhD thesis, MIT, AI Lab, Aug. 1993. Home/Search Document Details and Download
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A Register File Architecture and Compilation Scheme for .. - Kailas, Franklin.. (Correct)
....file structures used in prior clustered ILP processor architectures [9, 11, 4, 10, 2] are different from our CRB based scheme as explained in section 1. Caching of processor registers in general is not a new concept and has been used in different contexts such as the Named State Register file [16] and Register Use Cache [17] for multi threaded processors, the pipelined register cache [18] and Register Scoreboard and Cache [19] Our scheme is different from these as none of them are aimed at keeping a local copy of a remote register. Fernandes et al. 20] proposed a partitioned register ....
P. R. Nuth, The Named-State Register File. PhD thesis, MIT, AI Lab, Aug. 1993.
StarT the Next Generation: Integrating Global Caches and.. - Ang, Arvind, Chiou (1994) (18 citations) (Correct)
....latency operation [2] On the University of Tokyo s UNIRED II processor[35] the frequency of thread switching depends on the number of active threads. One might also allow one register file to be swapped while another is in use. Another possible related solution is the Named State Register File[25] which uses a cache instead of a register file and has multiple pipeline registers to allow very rapid switching between threads. Yet another solution is to permit multiple instruction streams to execute on the same set of execution units. If sufficient load store unit bandwidth is available, this ....
P. R. Nuth. The Named-State Register File. PhD thesis, Department of EECS, MIT, Cambridge MA, Aug 1993.
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