Y. Aimoto et al., "A 7.68 GIPS 3,84 GB/s 1W Parallel Image Processing RAM Integrating a 16 Mb DRAM and 128 Processors," Dig. Technical Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE, 1996, pp. 372-373, 476.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....in a 15.1 x 15.6 mm 2 die area. The chip operates at 40 MHz and has a peak processing performance of 2.56 GIPS and a peak memory bandwidth of 1.28 GBytes s. Figure 2.2 shows the configuration of the IMAP chip. As an improvement to IMAP, NEC developed the Parallel Image Processing RAM (PIP RAM) [12]. This logic in memory image processor integrates 128 PE s and 16 Mb DRAM in a 64 Mb DRAM process technology. As in IMAP, the PE is 8 bits and consists mainly of an 8 bit ALU, a shifter, 24 general purpose registers, and 5 special purpose registers. Each PE has 128 Kb of DRAM. The PIP RAM chip has ....

....have also been trimmed to only those required to control the rather simple singlebit CRAM PEs. General Purpose Architecture: In most logic in memory systems, the PE array and the controller are designed for specific applications. For example, the PE and the controller for IMAP[10] PIPRAM[12], and MIT PP[14] are designed specifically for 8bit pixel processing. FMPP VQ[16] can only run Vector Quantization, while the logicin memory graphics accelerator and frame buffer [18] has a controller that is hardwired for graphics operations only. On the other hand, the CRAM controller had to ....

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Yoshiharu Aimoto, et al, "A 7.68 GIPS 3.84 GB/s 1W Parallel Image-Processing RAM Integrating a 16 Mb DRAM and 128 Processors", IEEE International SolidState Circuits Conference, pp 372-373, February, 1996.

.... in a multiprocessor, IRAMs that include a MIMD (Multiple Instruction streams, Multiple Data streams) multiprocessor within a single chip [Fil95] Kog95] Mur97] and IRAMs that include a SIMD (Single Instruction stream, Multiple Data streams) multiprocessor, or array processor, within a single chip [Aim96] [Ell92] This category is the most popular research area for IRAMs. Figure 6 places uniprocessor and multiprocessor chips on a chart showing the amount hardware for memory on the X axis versus the amount of hardware for processing on the Y axis. The units of the X axis is bits of storage. The ....

Aimoto, Y.; Kimura, T.; Yabe,Y; Heiuchi, H.; and others. "A 7.68 GIPS 3,84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors". Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 8-10 Feb. 1996, p. 372-73, 476.

....broadcast logic and interface. Each CU has a 16 b data read back output to the broadcast logic. The CU read back data can be shifted out of the chip at a rate of two bits per clock cycle. When running at 25MHz, each chip delivers a performance of 50 MIPS. 2. 7 Parallel Image Processing (PIP RAM) [Aimoto96] The PIP RAM consists of 128 PE s and 128 DRAM elements (with 4 redundant PE DRAM pairs) a main word decoder (MWD) clock buffers, and control circuits (Fig.7) Each PE has a 8 b ALU, a shifter, 24 general purpose registers, 5 special purpose registers, and a DRAM element of 128Kb. The DRAM ....

Y. Aimoto, T. Kimura, Y. Yabe, "A 7.68GIPS 3.84GB/s 1W Parallel Image Processing RAM integrating a 16Mb DRAM and 128 Processors", ISSCC96, pp.372-373, 1996.

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Y. Aimoto et al., "A 7.68 GIPS 3,84 GB/s 1W Parallel Image Processing RAM Integrating a 16 Mb DRAM and 128 Processors," Dig. Technical Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE, 1996, pp. 372-373, 476.

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