B. S. Carlson and S.-J. Lee. Delay optimization of digital CMOS VLSI circuits by transistor reordering. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.14, (no.10), pages 1183-92, Oct. 1995 Home/Search Document Not in Database Summary Related Articles |
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A Timed Automaton-Based Method for Accurate.. - Tasiran, Khatri.. (1998) (1 citation) (Correct)
....the same effective size of transistors, the timed automaton for the gate will have n distinct rising delays, and m distinct falling delays. In general, for a k input gate, each of the 2 k Delta (2 k Gamma 1) input sequences give rise to distinct delays at the output, as was suggested in [CL95]. However, in practice, the delays are tightly clustered around the n m distinct values we use. For a general gate, we first determine the values of m and n. After this, we compute each distinct rise and fall delay by means of SPICE [N75] a transistorlevel simulator, which gives us the exact ....
B. S. Carlson and S.-J. Lee. Delay optimization of digital CMOS VLSI circuits by transistor reordering. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.14, (no.10), pages 1183-92, Oct. 1995
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