S. Chakravarty, "On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits," 27th Annual Allerton Conference on Communication, Control and Computing, pages 730-739, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the supervertices in an s graph should be processed in descending order of their weights. 4.2. 2 Variable Ordering for BDDs Once we have split the loops in the sequential circuit to form a combinational structure we are ready to use BDDs [1] to compute the signal probability at each circuit node [3, 14]. We can greatly reduce the complexity of BDD computations by maximizing sharing of nodes in the ROBDD. Domino blocks have the following properties that allow us to maximize BDD node sharing: 1) The circuits are highly flattened and a node s average fanout is high, 2) The overall circuit is ....

S. Chakravarty, "On the complexity of using BDDs for the synthesis and analysis of Boolean circuits," Allerton Conference on Communication, Control and Computing, pp. 730-739, 1989.

....using (10) with fi being given by (11) and P(fl = 1) is evaluated using both transition and static probabilities, as described in Section (2.3) Instead of enumerating disjoint covers, Binary Decision Diagrams (BDDs) 3] can be used for the calculation of signal probability. It has been shown in [6] and [11] that exact signal probability calculation for a given function can be performed by a linear traversal of a BDD representation of a logic function. We have implemented methods for signal probability calculation using BDDs. 3 Gate Delay Effects As mentioned above, for static CMOS ....

S. Chakravarty. On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits. In Proceedings of the 27 h Annual Aller- ton Conference on Communication, Control, and Computing, pages 730-739, September 1989.

.... the assumption that the values applied to each circuit input are temporally independent (that is, value of any input signal at time t is independent of its value at time t 1) we can write: E (sw) 2 prob(n) 1 prob(n) 2) Computing signal probabilities has attracted much attention [48] [10]. In the recent years, a computational procedure based on Ordered Binary Decision Diagrams (OBDDs) 6] has become widespread. In this method, which is known as the OBDD based method, the signal probability at the output of a node is calculated by first building an OBDD corresponding to the global ....

S. Chakravarty. " On the complexity of using BDDs for the synthesis and analysis of boolean circuits. " In Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing, pages 730--739, 1989.

....multiple output functions by allowing each single output to be rooted arbitrarily in the resulting shared BDD. 4 Switching Probability Estimation An output probability of a function, f , denoted as P [f ] is the probability that f has a value of 1 at some arbitrary time of observation [14, 6, 10]. Consider a function f having the output probability P [x] for the input variable x and the output probabilities P [f 0 ] and P [f 1 ] for the corresponding cofactors f 0 and f 1 . In terms of a BDD, this relationship is shown in Figure 1. P[f ] P[f ] f P[x] 0 1 x 1 0 Figure 1: Switching ....

S. Chakravarty. On the complexity of using BDDs for the synthesis and analysis of Boolean circuits. In Communication, Control and Computing, pages 730--739, 1989.

....probability of a function f as ffg. As an example, fx 1 x 2 x 3 g = 7 8 . The output probability of a function may be computed in time linear with respect to the size of a SBDD. Various algorithms have been developed that have complexity proportional to the number of vertices in the BDD [6] [11] and they are applicable to SBDDs with negative edge attributes [14] Since we are interested in using symmetry relations among the variables of a Boolean function, the relationship in Theorem 1 provides the connection between variable symmetry and output probabilities. Theorem 1 ff Phi x ....

.... x j implies that ff x i g = ff x j g. Thus, ffg fx i g Gamma ff x i g = ffg fx j g Gamma ff x j g This relationship can then be rewritten as: ff Phi x i g = ff Phi x j g 2 The output probabilities described here may be computed using algorithms that perform single traversals of SBDDs [6] [14] Thus, it is practical to compute the n probability values of ff Phi x i g for all x i 2 S. 2.2 Relationship of Variable Order and Output Probability During the formulation of this technique, we generated plots of ff Phi x i g versus the dependent variable index i for the best known ....

S. Chakravarty. On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits. Proceedings of the 27th Annual Allerton Conference on Communication, Control, and Computing, pages 730--739, 1989.

....(1) and (2) based on the temporal independence assumption. In general, if the circuit is built from Boolean components that are not part of a pre defined gate library, the signal probability can be computed on the fly by using a BDD [35] to represent the Boolean functions, as proposed in [25] and [37]. Since it uses a zero delay timing model, this method does not account for the glitch power. 3.2.2.2. Probabilistic simulation A probabilistic power estimation approach that does compute the glitch power and does not make the zero delay or temporal independence assumptions, called probabilistic ....

S. Chakravarty, "On the complexity of using BDDs for the synthesis and analysis of Boolean circuits," 27th Annual Allerton Conference on Communication, Control, and Computing, pp. 730--739, September 1989.

....use of (1) and (2) based on the temporal independence assumption. In general, if the circuit is built from Boolean components that are not part of a predefined gate library, the signal probability can be computed by using a BDD [35] to represent the Boolean functions, as proposed in [10] and [37]. As an example to illustrate the BDD representation, consider the Boolean function y = x 1 x 2 x 3 , which can be represented by the BDD shown in Fig. 3. The Boolean variables x i are ordered, and each level in the BDD corresponds to a single variable. Each level may contain one or more BDD ....

S. Chakravarty, "On the complexity of using BDDs for the synthesis and analysis of Boolean circuits," 27th Annual Allerton Conference on Communication, Control, and Computing, pp. 730--739, Monticello, IL, September 27--29, 1989.

....use of (1) and (2) based on the temporal independence assumption. In general, if the circuit is built from Boolean components that are not part of a predefined gate library, the signal probability can be computed by using a BDD [35] to represent the Boolean functions, as proposed in [10] and [37]. As an example to illustrate the BDD representation, consider the Boolean function y = x 1 x 2 x 3 , which can be represented by the BDD shown in Fig. 3. The Boolean variables x i are ordered, and each level in the BDD corresponds to a single variable. Each level may contain one or more BDD ....

S. Chakravarty, "On the complexity of using BDDs for the synthesis and analysis of Boolean circuits," 27th Annual Allerton Conference on Communication, Control, and Computing, pp. 730--739, Monticello, IL, September 27--29, 1989.

....circuitry [9] Several exact and approximate methods for the determination of circuit output probabilities have been developed. Algebraic and circuit topology based methods were proposed in the original paper [8] and later a method using ordered binary decision diagrams (OBDDs) was proposed in [3]. Some of the estimation methods developed include those discussed in [11] The OBDD based method in [3] can be used to compute the output probabilities in a very efficient manner if the candidate circuit is described using a compact OBDD. It is proven that the asymptotic complexity of this method ....

....have been developed. Algebraic and circuit topology based methods were proposed in the original paper [8] and later a method using ordered binary decision diagrams (OBDDs) was proposed in [3] Some of the estimation methods developed include those discussed in [11] The OBDD based method in [3] can be used to compute the output probabilities in a very efficient manner if the candidate circuit is described using a compact OBDD. It is proven that the asymptotic complexity of this method is O(N ) where N is the number of vertices in the OBDD. This methodology is a based upon a ....

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S. Chakravarty. On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits. Proceedings of the 27th Annual Allerton Conference on Communication, Control, and Computing, pages 730--739, 1989.

.... using Shannon s expansion [3] The cutting algorithm, which computes lower and upper bounds on the signal probability of reconvergent nodes was developed and presented in [4] Also, the Ordered Binary Decision Diagram representation (OBDD) was used for computing the signal probability in [6] and [7] The spatial correlations among different signals are modelled in [5] where a procedure is described for propagating signal probabilities from the circuit inputs toward the circuit outputs using only pairwise correlations between signals and ignoring higher order correlation terms. None ....

....probability is: Since path p is fixed, the above probability may be computed on the OBDD in the same way as a signal probability. The idea is that, using Shannon decomposition, the signal probability (and hence the above probability) may be computed in linear time in the number of the OBDD nodes [6]. Thus, may be decomposed as follows: 25) where are the cofactors with respect to x k and x k , respectively. Based on this recursive decomposition, we may also write a similar relation for the corresponding probabilities, taking also into account the possible existing correlations: 26) Having ....

S.Chakravarty, `On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits', in Proc. of the 27th Annual Allerton Conf. on Comm., Control and Computing, 1989

....sum of the leakage power for each input combination, with the weights being the probability of the corresponding input combination. Consequently, to accurately estimate the leakage power, the exact probabilities for each input combination have to be found. These may be computed exactly using BDDs[6]. However, in most practical cases, the signal probabilities at the gate inputs and outputs are obtained by either local probability propagation or by logic simulation. An accurate and computationally efficient model for a short channel MOSFET is described in [4] The model, called the nth power ....

S. Chakravarty, "On the complexity of using BDDs for the synthesis and analysis of Boolean circuits," Proc. of the 27th Annual Allerton Conference on Communicatio, Control, and Computing, pp. 730-739.

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S. Chakravarty, "On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits," 27th Annual Allerton Conference on Communication, Control and Computing, pages 730-739, 1989.

No context found.

S. Chakravarty, "On the complexity of using BDDs for the synthesis and analysis of boolean circuits.", in Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing, pp 730-739, 1989

No context found.

S. Chakravarty. On the complexity of using BDDs for the synthesis and analysis of boolean circuits. In Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing, pages 730--739, 1989.

No context found.

S. Chakravarty. " On the complexity of using BDDs for the synthesis and analysis of boolean circuits. " In Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing, pages 730--739, 1989.

No context found.

S. Chakravarty. " On the complexity of using BDDs for the synthesis and analysis of boolean circuits. " In Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing, pages 730--739, 1989.

No context found.

S. Chakravarty. On the complexity of using bdds for the synthesis and analysis of boolean circuits. InAllerton Conference on Communication, Control and Computing, pages 73(739, 1989.

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