D. Sima, T. Fountain, and P. Kacsuck. Advanced Computer Architectures: a Design Space Approach. Addison-Wesley, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....are used to give the correct ordering to the simulation of the phases of the execution of instructions of pipelined processors. Well known problems such as pipeline stalls caused by RAW dependencies and their typical solutions such as bypassing used to solve de ne use and load use con icts [15] could be speci ed and simulated in our rewriting logic approach. 4 Results 4.1 Rewriting logic based simulation The natural separation available in ELAN between rewriting and logic strategies makes it possible to control in an adequate way the application of rules and for many aspects of ....

....to be executed must be taken according to the contents in a table known as the branch template bu er (BTB) Some well known dynamic branch prediction schemes are easy to simulate by including simple rewrite rules. We mention two of these that are called 1 bit and 2 bit dynamic prediction [15]. An initial prediction is given in the BTB. You can explicitly give, for instance, pairs (1; 2) j; j 1) n; n 1) meaning that after execution of each rule the initial prediction is to jump 8 Size 10 ran 10 ord 20 ran 20 ord 30 ran 30 ord 1 bit correct 51 60 128 225 218 490 ....

D. Sima, T. Fountain, and P. Kacsuck. Advanced Computer Architectures: a Design Space Approach. Addison-Wesley, 1997.

.... the Alpha 21164 [Bannon97, Edmondson95] and 21264 [Kessler98, Kessler99, Leiholz97, Matson98] the UltraSparc I [Tremblay96] II [Normoyle98] and III [Horel99] HP PA 8000 [Kumar97] the PowerPC 604 [Song94] and the MIPS R10000 [Yeager96] To fill in the gaps left by the aforementioned papers, [Silc99, Sima97] and several web searches were also used as references. Based on the range of reasonable values, we chose a low and high value for each parameter. Tables 6, 7, and 8 show the final values for each of the relevant parameters for the processor core, the functional units, and the memory hierarchy, ....

D. Sima, T. Fountain, and P. Kacsuk; "Advanced Computer Architectures, A Design Space Approach"; Addison Wesley Longman, 1997.

....those found in several commercial processors. Our list of commercial processors included the Alpha 21164 [1, 6] and 21264 [12, 13, 16, 18] the UltraSparc I [29] II [21] and III [11] the HP PA 8000 [15] the PowerPC 604 [28] and the MIPS R10000 [30] To fill in the gaps left by these papers, [24, 25] and several web searches were also used as references. Tables 3, 4, and 5 show the final values for each of the relevant parameters in the processor core, the functional units, and the memory hierarchy, respectively. A couple of parameters across all three tables are shaded in gray. For these ....

D. Sima, T. Fountain, and P. Kacsuk, "Advanced Computer Architectures, A Design Space Approach", Addison Wesley Longman, 1997.

....reduces all the hardware needed compared to a dynamic scheduling approach. Further reading and a more detailed explanation and description on pipelining, superscalar pipelining, dynamic scheduling and VLIW packing, along with advantages and limitations of each one, can be found in [5] 6] 7] 8][9]. 2.1.2 SRAM based programming technology An FPGA (Field Programmable Gate Array) is a general purpose, multi level, programmable device with a very high logic density, that allows the user to implement logic circuits in a very short period. It consists of an array of unconnected logic blocks ....

....on the data and store back the resulting vector into memory. This architecture allows very deep pipelines and eliminates many of the data and control hazards in a program. Newer vector architectures perform operations on registers rather than memory. More on vector architectures can be found in [8][9]. OTHER COMPILER OPTIMIZATIONS Other compiler optimizations exist that allow a much simpler circuit implementation. Among them are, Strength Reduction and Register Renaming. Strength reduction replaces expensive operations, such as multiplications and divisions, by less expensive ones, such as ....

Sima, D., T. Fountain and P. Kacsuk. Advanced Computer Architectures: A Design Space Approach. Addison-Wesley Publishing Company, USA, 1997.

....Chapter 2 ILP Architectures and the OCEANS Compiler Parallelism is one of the hottest ideas in computing. Architectures, compilers and operation systems have been striving for more than two decades to extract and utilize as much parallelism as possible in order to speed up computation. SFK97] Parallelism available at different levels can be classified into two categories: ffl Fine grained parallelism That is the parallelism available at instruction level(or say at machine language level) by means of executing instructions simultaneously. Instruction level parallelism, commonly ....

....most widely used computer architectures as well as high level programming languages. Von Neumann computational model has been proposed by Von Neumann and his colleagues in 1946, whose key characteristics result from the multiple assignments of variables and from the control driven execution [SFK97] Multiple assignments means that the variables can be assigned new values as many times as required during the execution. In other words, the variables keep their values until an operation modifies them 2 . Hence, in the different point of program execution, the variables have possibly ....

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D. Sima, T. Fountain, and P. Kacsuk. Advanced computer architectures: A design space approach. Addison Wesley, 1997.

....a simpli ed view of SIMD operation, the PEs execute synchronously instructions broadcast by the controller while the controller is responsible not only for driving the array but also for executing the primary thread of control. For details about many aspects of SIMD array architecture see, e.g. [31]. We now give an overview of SIMD array system design issues. PE design One characteristic of SIMD arrays is that PEs do not have individual micro sequencers or much other control circuitry; rather their CPUs consist almost entirely of datapath. A wide range of PEs has been implemented: the ....

Sima, D., Fountain, T., and Kacsuk, P. Advanced Computer Architectures: A Design Space Approach. AddisonWesley, Harlow, England, 1997.

.... For example, the MGAP does not have even a complete one bit ALU [14] while the MasPar MP2 contains a 32 bit datapath and extensive floating point support [2] Also, although no SIMD array has yet been built with PE cache, studies have shown the clear benefits [13, 1] For details see, e.g. [17]. Several factors have converged to now make SIMD arrays extremely attractive. ffl Finding niche areas. Among these are graphics (e.g. the HP VISUALIZE PxFl) compression [20] neural nets [15] image processing [3, 7, 16] DSP [5] MMX, and chess (the Deep Blue coprocessors) ffl Avoiding the ....

Sima, D., Fountain, T., and Kacsuk, P. Advanced Computer Architectures: A Design Space Approach. Addison-Wesley, Harlow, England, 1997.

.... Institute of Computer Science, Polish Academy of Sciences ul. Ordona 21, 01 237 Warsaw, Poland e mail: tudruj ipipan.waw.pl 1. Introduction In contemporary parallel programming techniques, the need for automated parallel process synchronization implementation is becoming more and more justified [1 4, 8]. The rationale for inclusion of synchronization primitives into parallel programming environments comes from three main domains: parallel algorithm design which involves synchronization of constituent actions, parallel program execution paradigms which include synchronization as a well ....

Sima D., Fountain T. and Kacsuk P.: Advanced Computer Architectures - A Design Space Approach, Addison-Wesley, 1997, pp. 766

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D. Sima, T. Fountain, and P. Kacsuck. Advanced Computer Architectures: a Design Space Approach. Addison-Wesley, 1997.

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D. Sima, T. Fountain, and P. Kacsuck. Advanced Computer Architectures: a Design Space Approach. Addison-Wesley, 1997.

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D. Sima, T. Fountain, and P. Kacsuck. Advanced Computer Architectures: a Design Space Approach. Addison-Wesley, 1997.

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D. Sima, T. Fountain, and P. Kacsuk, "Advanced Computer Architectures, A Design Space Approach", Addison Wesley Longman, 1997.

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D. Sima, T. Fountain, and P. Kacsuk, "Advanced Computer Architectures, A Design Space Approach", Addison Wesley Longman, 1997.

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