T. Komuro, I. Ishii, and M. Ishikawa. Vision Chip Architecture Using GeneralPurpose Processing Elements for 1ms Vision System. In Proceedings of the Fourth IEEE International Workshop on Computer Architectures for Machine Perception, pages 276--279,Cambridge, MA, Oct. 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....decoding, if necessary. We expose in this paper our design strategy to get the most compact yet computationally powerful enough PE. From this point of view, the order in which we have presented the five above duties is highly meaningful. Considering the few PARs that have previously been reported [6 9], it indeed appears that the choices made about data storage are of central importance. Indeed, it is by far the most transistor consuming duty among the five above. Furthermore, it affects most other aspects of the PE, thus structuring the whole design. In fact, data communication cannot be ....

....the solution we have chosen. To make RAM based solutions more compact, one may think that incorporating decoders in the PE will decrease AW while not increasing AL too much. The number of global wires would indeed be smaller, however local connections would be more complex. The design reported in [9] uses this strategy. But this version corresponds to the early days of the project, explaining some poor figures on the fourth line of table 1. If based on the same principles, the upcoming version will allow to get a more precise estimate of the area savings of shift register compared with RAM ....

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T. Komuro, I. Ishii, and M. Ishikawa. Vision chip architecture using general-purpose processing elements for 1ms vision system. In C. Weems, editor, Proc. Workshop on Computer Architecture for Machine Perception, pages 276-279, Boston, MA, USA, October 1997. IEEE Computer Society Press.

....array processor with an imaging array implies the existence of three facilities within each pixel: storage, communication and computation. Because of parasitic photocurrents that exist in the substrate of a retina, data storage is better made static. A standard solution, used by other teams [4, 9], is to settle a tiny RAM in each pixel, built with static RAM cells, each of which acts as a binary register. Another solution the one we have chosen [15] is to use a most simplified version of the D flip flop, called the semi static binary register which appears on figure 2. The latter ....

T. Komuro, I. Ishii, and M. Ishikawa. Vision chip architecture using general-purpose processing elements for 1ms vision system. In C. Weems, editor, Proc. Workshop on Computer Architecture for Machine Perception, pages 276--279, Boston, MA, USA, October 1997. IEEE Computer Society Press.

.... solved this problem, however: a board level instruction issue rate of 100MHz was achieved in 1995 by Bolotski s Abacus [3] and systems with a chip level issue rate of 200MHz are commercially available from PixelFusion [28] The likely applications continue to be graphics [28, 36] and vision [4, 10, 24, 21] although compression [41] neural nets [23] chess (the IBM Deep Blue coprocessors) and scienti c computing [32] are some of the other possibilities. Corresponding to the increased capabilities of single chip (or single substrate) SIMD arrays is an increase in design choices; yet, no adequate ....

Komuro, T., Ishii, I., and Ishikawa, M. Vision chip architecture using general-purpose processing elements for 1ms vision system. In Proc. of Computer Architectures for Machine Perception `97 (1997), pp. 276-279.

....PE cache, studies have shown the clear benefits [13, 1] For details see, e.g. 17] Several factors have converged to now make SIMD arrays extremely attractive. ffl Finding niche areas. Among these are graphics (e.g. the HP VISUALIZE PxFl) compression [20] neural nets [15] image processing [3, 7, 16], DSP [5] MMX, and chess (the Deep Blue coprocessors) ffl Avoiding the memory wall by building PEs onto memory cores. Although integrating processing and memory is an old idea (see e.g. 6] the latest projects have access to current technology and are yielding impressive results. See e.g. 9, ....

Komuro, T., Ishii, I., and Ishikawa, M. Vision chip architecture using general-purpose processing elements for 1ms vision system. In Proc. of Computer Architectures for Machine Perception `97 (1997), pp. 276--279.

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Komuro, T., Ishii, I., and Ishikawa, M. (1997). Vision chip architecture using general-purpose processing elements for 1ms vision system. Proc. IEEE Int. Workshop on Computer Architecture for Machine Perception, pages 276--279.

....[2] In these researches it was as sumed that motion of an object was known beforehand. For this reason there was a problem in that the system could not complete a task in an unknown environment. On the other hand, vision chip systems have recently been developed for high speed visual processing [3, 4]. Because they have a parallel processing architecture in which each photodetector is directly connected to a corresponding processing element, visual processing is re alized at a high rate [5, 6] The use of such high speed vision in manipulation can solve the problem of the delay of visual ....

.... is perfectly executed in parallel, high speed visual feed back is realized within lms [5] The SPE 256 is a scale up model of an integrated vision chip and the next generation is currently being developed in which all elements of the vision chip archi tecture are integrated in one chip [4]. The actuator part of the active vision subsystem has two degrees of freedom; pan and tilt. This is used to move the sensor platform and this is controlled by a DSP assigned for active vision control. 3.3 axis Manipulator with Dextrous Multi fingered Hand The hand arm subsystem is a 7 axis ....

T. Komuro, I. Ishii, and M. Ishikawa. Vision chip architecture using general-purpose processing elements for lms vision system. Proc. Jth IEEE Int. Workshop on Computer Architecture for Machine Perception (CAMP'97), pages 276-279, 1997.

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T. Komuro, I. Ishii, and M. Ishikawa. Vision Chip Architecture Using GeneralPurpose Processing Elements for 1ms Vision System. In Proceedings of the Fourth IEEE International Workshop on Computer Architectures for Machine Perception, pages 276--279,Cambridge, MA, Oct. 1997.

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