D. K. Arvind, R. D. Mullins, and V. E. F. Rebello. Micronets: A model for decentralising control in asynchronous processor architectures. In M. B. Josephs, editor, The Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, pages 190--199, London, UK, May 1995. IEEE Computer Society Press. Home/Search Document Details and Download
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Simulation of Asynchronous Instruction Pipelines - Chia-Hsing Chien (1996) (Correct)
.... advantages associated with asynchronous design are discussed in more detail in [9, 10] At the Second Working Conference on Asynchronous Design Methodologies (1995) several additional asynchronous machine designs were proposed although the performance of these machines is still not clear [17, 1, 7]. The simulation tool ARAS is designed to help evaluated the performance of alternative asynchronous architectures. Thus, evaluations can be obtained prior to implementing the real machine. Section 2 below presents an overview of the ARAS simulator and how it is used. Section 3 discusses the data ....
D.K. Arvind, R.D. Mullins, and V.E.F. Rebello. Micronets: A Model for Decentralising Control in Asynchronous Processor Architectures. In 2nd Working Conference on Asynchronous Design Methodologies, London, England, May 1995.
Static Scheduling of Instructions on Micronet-based.. - Arvind And Rebello Self-citation (Arvind Rebello) (Correct)
....model, such as scheduling instructions in execution gaps, are less effective. A micronet is a network of pipelines, with (selected) stages of different pipelines being able to communicate with each other. This enables the exploitation of both spatial and temporal concurrency between instructions [2] (in contrast, a micropipeline only exploits temporal parallelism [4] It is more difficult for a compiler to predict the behaviour of the micronet for the following reasons: firstly, as in a micropipeline the delay of each pipeline stage might vary; secondly and more uniquely, each instruction ....
....micro operations for an instruction are initiated independently by the issue unit, as soon as their particular microagents become available, and delegates all control to them, thus freeing the issue unit for the next instruction. Therefore, the idle time between instructions is kept to a minimum [2]. The executing instructions also release their microagents individually, as soon as the respective micro operations have completed, thus freeing the resources immediately for another instruction. Finally, through a novel application of the communication protocol, datapath hazards are resolved ....
D. K. Arvind, R. D. Mullins, and V. E. F. Rebello. Micronets: A model for decentralising control in asynchronous processor architectures. In M. B. Josephs, editor, The Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies, pages 190--199, London, UK, May 1995. IEEE Computer Society Press.
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