. M. A. Schutte, J. P. Shen, D. P. Siewiorek, Y. X. Zbu, "Experimental Evaluation of Two Concurrent Error Detection Schemes", 16 International Symposium on Fault Tolerant Computing (FTCS- 16), pp. 138-143, 1986  Home/Search   Document Not in Database   Summary   Related Articles   Check

....comparison utilize new technologies in processors to reduce the time overhead [ 10] Although most studies on time redundancy focus on detecting errors, some studies have addressed the use of triplicated execution and voting to mask errors on a single node. Triplicated execution is evaluated in [11], where each sofl vare module and the voting mechanisms are executed three times to mask errors. Another approach using time redundancy is roll back recovery [12] In roll back recovery, the error is detected by various error detection mechanisms and additional time is used to re execute the ....

Schuette, M.A., Shen J.P., Siewiorek D.P., and Zhu Y.X., "Experimental Evaluation of Two Concurrent Error Detection Schemes", in FTCS Digest of Papers. 16th Annual Int'l Syrup. on Fault-Tolerant Computing Systems, Washington, DC, USA, 1986, pp. 138-143.

....by Yau and Chen [Yau80] outlined the general control flow checking scheme using the program specification language PDL. Mahmood [Mah88] presents a survey of the various techniques in hardware for detecting controlflow errors. Many schemes for checking control flow in hardware have been proposed [Nam82, Sch86, Wil90, Mad91, Mic91, Upa94, Mir95]. A summary of some of these techniques is presented in Table 2. The basic scheme is to divide the application program into blocks. Each block has a single entry and a single exit point. A golden (or reference) signature is associated with the block that represents an encoding of the correct ....

....by comparing the runtime and the golden signatures of the block. Among the hardware schemes, two broad classes of techniques have been defined that access the precomputed signature in two different ways. Embedded Signature Monitoring (ESM) embeds the signature in the application program itself [Wil90, Sch86], while Autonomous Signature Monitoring (ASM) stores the signature in memory dedicated to the watchdog processor [Mic91] Upadhyaya et al. Upa94] explore an approach in which no reference signatures need be stored, and the runtime signature is any m out of n code word. Applying hardware schemes ....

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M.A. Schuette, J.P. Shen, D.P. Siewiorek, and Y.X. Zhu, "Experimental Evaluation of Two Concurrent Error Detection Schemes," Digest of Papers, 16 Int. Symposium on Fault-Tolerant Computing, 138-143, July 1986.

....of confidence that the measured factor represents the actual coverage. One method used to address the above question is Physical Fault Injection. This technique places physical faults in the system under test and observes the resulting error or failure response [Crou82] Lala83] Damm88] Schu86] Gunn87] Coverage Measurement Statistics The behavior of a system in the presence of faults can be determined through a suitably selected set of proportion sample tests. Each test induces a fault in the system and the resulting behavior is observed. From these sample tests an inference can ....

Schutette, M. A., Shen J. P., Siewiorek, D. P., and Zhu, Y. X., "Experimental Evaluation of Two Concurrent Error Detection Schemes," International Symposium on Fault--Tolerant Computing, July 1986, pp. 138--143.

....to validate their implementation in a fault tolerant system. Until recently, most studies related to the application of fault injection on a prototype of a fault tolerant system relied on physical fault injection, i.e. the introduction of faults through the hardware layer of the target system [1, 5, 18] . A trend favouring the injection of errors through the software layer for simulating physical faults (i.e. software implemented fault injection) has recently emerged (e.g. see [7, 19] Although such an approach facilitates the application of fault injection, the correspondence between the ....

....i.e. the injection of faults directly on the pins of the ICs of a prototype was until now the most widely applied physical fault injection technique. It has been used for (i) the evaluation of the coverage of specific mechanisms (in particular for error detection by means of signature analysis [18] , and (ii) the validation of fault tolerant distributed systems (e.g. 2, 21] Flexible tools supporting some general features have been developed (e.g. the test facility used on the FTMP [12] MESSALINE at LAAS CNRS [1] or RIFLE [13] at the University of Coimbra) The tool MESSALINE that ....

M. A. Schuette, J. P. Shen, D. P. Siewiorek and Y. X. Zhu, "Experimental Evaluation of Two Concurrent Error Detection Schemes", in Proc. 16th Int. Symp. Fault-Tolerant Computing (FTCS-16), (Vienna, Austria), pp.138-43, IEEE Computer Society Press, 1986.

....The injection of faults directly on the pins of the ICs of a prototype was until now the most widely applied physical fault injection technique. It has been used for (i) the evaluation of the coverage of specific mechanisms (in particular for error detection by means of signature analysis [5], and (ii) the validation of fault tolerant distributed systems (e.g. 6, 7] Flexible tools supporting some general features have been developed (e.g. the test facility used on the FTMP [8] MESSALINE at LAAS CNRS [9] or RIFLE [10] at the University of Coimbra) The tool MESSALINE that was ....

M. A. Schuette, J. P. Shen, D. P. Siewiorek and Y. X. Zhu, "Experimental Evaluation of Two Concurrent Error Detection Schemes", in Proc. FTCS-16, Vienna, Austria, 1986, pp. 138-143 (IEEE Computer Society Press).

....system and plugged into separate boxes. A successful study showing the strength of the pin level insertion technique for experi Equipotential line Target IC Stuck at Fault Chapter 2 Fault Injection for Dependability Validation 13 mental validation of error detection mechanisms is given in [Schuette et al. 1986]. The error detection schemes Software Triple Modular Redundancy (STMR) and Signatured Instruction Streams (SIS) both implemented using the MC68000 CPU, are evaluated by injecting inversion faults with a duration of one to four clock cycles on the pins of the CPU. The results show that STMR is ....

.... 1994] B MEFISTO DP32 [Sieh et al. 1997] A VERIFY DP32 Simulation based (function level) Goswami and Iyer 1991] C DEPEND Tandem Integrity S2 Pin level forcing [Arlat et al. 1990] BC MESSALINE PAI, Delta 4 [Walter 1990] BC MAFT [Arlat et al. 1993] C MESSALINE Delta 4 Pin level insertion [Schuette et al. 1986] C MC68000 [Madeira et al. 1991] B RIFLE [Steininger and Scherrer 1997] C SCRIBO Heavy ion radiation using cyclotrons [Koga and Kolasinski 1984] C [Gaisler 1997] C ERC32 Heavy ion radiation using Cf 252 [Gunneo et al. 1989] C FIST MC6809E [Karlsson et al. 1994] AB FIST MC6809E [Lidn et ....

[Article contains additional citation context not shown here]

M. A. Schuette, J. P. Shen, D. P. Siewiorek and Y. X. Zhu, Experimental Evaluation of Two Concurrent Error Detection Schemes, in Proc. 16th Int. Symp. Fault-Tolerant Computing (FTCS-16), pp. 138-143, (Vienna, Austria), 1986.

....fault injection is the most widely used physical fault injection technique. It has been used for validating fault tolerant distributed computer systems (e.g. Damm 1986; Walter 1990] and for evaluating the coverage of specific mechanisms such as error detection by means of signature analysis [Schuette et al. 1986]. Figure 6: Pin level fault injection using forcing In this technique, faults are injected on the pins of the ICs of the tested system. A variety of fault models is used; e.g. stuck at 0 or 1, in which the faulted pins are set to a logic 0 or 1, bridging, when several pins of a circuit are ....

M. A. Schuette, J. P. Shen, D. P. Siewiorek and Y. X. Zhu, "Experimental Evaluation of Two Concurrent Error Detection Schemes", in Proc. 16th Int. Symp. Fault-Tolerant Computing (FTCS-16), (Vienna, Austria), pp.138-43, IEEE Computer Society Press, 1986.

....fault injection experiments on the JPL Star computer. Besides the pin level faultinjection also heavy ion radiation and power supply disturbances have been used for physical fault injection experiments to provide for more realistic faults in those experiments. 2.1. 1 Pin Level Fault Injection In [SSSZ86] a fault inserter is presented which can be programmed to insert inversion faults of Page 4 of 11 1, 2 or 4 cycle length on 11 different pins of the data and address bus of a MC68000 processor. Another pin level fault injecting system called MESSALINE is presented in [ACL89] MESSALINE is a ....

M.A. Schuette, J.P. Shen, D.P. Siewiorek and Y.X. Zhu. "Experimental Evaluation of Two Concurrent Error Detection Schemes" 16th International Symposium on Fault-Tolerant Computing, p. 138-143

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. M. A. Schutte, J. P. Shen, D. P. Siewiorek, Y. X. Zbu, "Experimental Evaluation of Two Concurrent Error Detection Schemes", 16 International Symposium on Fault Tolerant Computing (FTCS- 16), pp. 138-143, 1986

No context found.

Schuette, M., Shen, J., Siewiorek, D. & Zhu, Y., "Experimental evaluation of two concurrent error detection schemes," Digest of Papers. 16th Annual International Symposium on Fault-Tolerant Computing Systems, Vienna, Austria; 1-4 July 1986, pp. 138-43

No context found.

M. Schuette, J. Shen, D. Siewiorek and Y. Zhu, "Experimental Evaluation of Two Concurrent Error Detection Schemes", Proceedings of the 16th Int. Symposium on Fault-Tolerant Computing (FTCS-16), IEEE, Vienna, Austria, June 1986, pages 138-143.

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