S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....has the advantages of both fast run times, as well as the ability to handle limited interconnections. To apply iterative bipartitioning to an arbitrary topology, we have developed an algorithm to automatically decide the order of the partitionings necessary to optimize to an arbitrary topology [Hauck95c]. We then can apply our bipartitioning algorithm, which is based on the Fiduccia Mattheyses variant of the Kernighan Lin algorithm [Hauck95b] Our optimized version of this algorithm is quite fast, and yields results significantly better than the current state of the art. After partitioning and ....

....reduced I O pin usage [Hauck94a] With this we have gained an understanding of how the Springbok baseplates and standard daughter cards should be constructed, though we have not yet fabricated the actual hardware. We have also examined how the external interfaces of a prototype can be supported [Hauck95c]. On the software end of the Springbok system, we have completed work on an efficient bipartitioning algorithm [Hauck95b] as well as methods for recursively applying bipartitioning to an arbitrary topology [Hauck95c] We have also developed pin assignment software [Hauck94b, Hauck94c] which ....

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S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, 1995.

....sub circuits using a pre partition routability prediction mechanism. 11] presents a set cover based approach for minimizing the delay of the partitioned design. Limited logic duplication is used to minimize the number of chip crossings on each circuit path. Bi partition orderings are studied in [5] to minimize critical bottlenecks during inter fpga routing. 8] 9] and [10] are primarily limited to device area and pin constraints. In [10] and [9] a library of fpgas is available and the objective is to minimize device cost and interconnect complexity. Functional replication techniques are ....

S. Hauck, G. Borriello. "Logic Partition Orderings for Multi-FPGA Systems". In Proc. of 3rd Int. Symp. FPGAs, pages 32--38, 1995.

.... remaining in the multi FPGA system, and after each partitioning the placement of the logic is restricted to a subset of the topology (labeling on circuit partitions) The greediness of iterative bipartitioning can be taken advantage of in order to map onto a specific multi FPGA topology [Hauck95b] Specifically, the multi FPGA topology itself will have some bottleneck in its topology, some place where the expected communication is much greater than the routing resources in the multi FPGA topology. For example, going back to the linear array of FPGAs discussed earlier (Figure 6) it is ....

S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 32-38, February, 1995.

....of the new groups are checked to determine if they should be further subdivided. For our purposes, the maximum allowable cluster size is equal to 1 of the total circuit size. There are several alterations that can be made to this algorithm to boost performance, details of which can be found in [Hauck95]. Before describing the last clustering method, it is necessary to discuss how to calculate the size of a logic node in the circuit being clustered. One possibility is to simply assume that all logic functions are the same size, and assign an area of 1 to all nodes. However, in many cases the ....

S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems", International Symposium on Field-Programmable Gate Arrays , pp. 32-38, 1995.

....original algorithm limits the number of subpartitions of any one group. Since this is not an important issue for our purposes, it was not included in our implementation. There are several alterations that can be made to this algorithm to boost performance, details of which can be found elsewhere [19]. Once the algorithm splits up a group into subpartitions, the sizes of the new groups are checked to determine if they should be further subdivided. For our purposes, the maximum allowable cluster size is equal to (total circuit size) 100, which is half the maximum partition size variation. ....

S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems", International Symposium on Field-Programmable Gate Arrays, 1995.

....the original algorithm limits the number of partitions of any one group. Since this is not an important issue for our purposes, it was not included in our implementation. There are several alterations that can be made to this algorithm to boost performance, details of which can be found elsewhere [Hauck95]. Once the algorithm splits up a group into subpartitions, the size of the new groups are checked to determine if they should be further subdivided. For our purposes, the maximum allowable cluster size is equal to (total circuit size) 100, which is half the maximum partition size variation. Before ....

S. Hauck, G. Borriello, "Logic Partition Orderings for Multi-FPGA Systems", submitted to International Workshop on Field-Programmable Gate Arrays, 1995.

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S. Hauck and G. Borriello. "Logic Partition Orderings for Multi-FPGA Systems", Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, pp. 32-38, February, 1995.

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S. Hauck and G. Borriello. "Logic Partition Orderings for Multi-FPGA Systems", Proceedings of the ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, Monterey, CA, pp. 32-38, February, 1995.

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