M. Srivastava, M. Potkonjak. Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-Based Approach. DAC'96, Las Vegas, NV, June 1996, pp. 343-348.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Gerlach gerlach informatik.uni tuebingen.de Wolfgang Rosenstiel rosenstiel informatik.uni tuebingen.de 1. This work was partially funded by the DFG Priority Research Program Rapid Prototyping of Embedded Systems With Hard Time Constraints . designer [4] or in a script oriented fashion [9]. In both strategies, the transformation results heavily depend on the experience of the human designer or script writer. Approaches on automated control of the transformation process are usually restricted to fixed optimization goals, e.g. area [7] or power [6] fixed target architectures, e.g. ....

M. Srivastava, M. Potkonjak. Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-Based Approach. DAC'96, Las Vegas, NV, June 1996, pp. 343-348.

....hardware software systems has begun to focus on reducing the power consumption of the systems being produced. Attention has been focused on reducing transition counts in the logic hardware using behavioral synthesis techniques [Rag94] Meh96] reducing memory accesses [Cat97] code generation [Tiw94][Sri96], and shutting down unused parts of a system [Mon96] Our goal is to examine power tradeoffs that can be made in the exploration of the design space. Consider the design of a 4 tap finite impulse response (FIR) filter. The most customized implementation of it is an ASIC that only executes this ....

M. Srivastava and M. Potkonjak, "Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach," Proc. of DAC `96, pp. 434-348, June 1996.

....Inaddition,wesupportpower optimizing transformations,unlikecompiler relatedoptimizationtechniques forwhichspeedistheprimaryobjective. Inhigh levelsynthesis,transformationsforthroughputand poweroptimizationfordata flowintensive(DFI)behavioraldescriptions [5] [6],aswellascontrol flowintensive(CFI)behaviors [7] 8]havebeenpresented.NoneofthesetransformationtechniquesforCFIbehaviorstargetspoweroptimization. Withtheexceptionof [8] thesesystemsdonotincorporateschedulinginformationintothetransformationapplicationprocess. ....

M. B. Srivastava and M. Potkonjak, "Power optimization in programmable processors and ASIC implementations of linear systems: Transformation-based approach ," in Proc. Design Automation Conf., pp. 343--348, June 1996.

....design while they are not used. Monteiro [14] et.al. present a scheduling algorithm that exploits the slack of operations to obtain a schedule that allows to manage power in this way. The savings reported amount to roughly 40 . A more specialized approach is introduced by Srivastava and Potkonjak [15]. They minimize power in linear systems unfolding the computations and implementing them maximally fast. This allows to reduce the supply voltage, which reduces the power consumption by a factor of 2.7 in a single processor implementation and by a factor of 15.6 in the multiprocessor case. In the ....

M. Srivastava, M. Potkonjak, Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-Based Approach, Proc. 33rd Design Automation Conference, June 1996, Las Vegas, Nevada

....transformations, unlike compiler related optimization techniques for which speed is the primary objective. In high level synthesis, transformations for throughput and power optimization for data flow intensive (DFI) behavioral descriptions is a well researched problem [8] 9] 10] 11] [12], 13] Transformations for CFI behaviors are considered in [14] 15] 16] In [14] loop merging and loop unrolling are used, followed by a greedy application of tree height reduction and constant propagation. In [15] procedure inlining, redundant code elimination, and pipelining are used. In ....

M. B. Srivastava and M. Potkonjak, "Power optimization in programmable processors and ASIC implementations of linear systems: Transformation-based approach ," in Proc. Design Automation Conf., pp. 343--348, June 1996.

....platforms. The main technical innovation of the research presented in this paper is the first approach for the minimization of the number of operations in general computations. The approach does not treat just significantly wide set of computations than the other previously published techniques [15], but also 7 8 6 9 10 A C D E B Figure 1: A motivational example outperforms or performs at least as well as other techniques on all examples. 1.2 Introductory Example Among the three main sources of power consumption in digital CMOS circuits which are switching power, short circuit power and ....

....there is an arc from a subpart X to a subpart Y, every output and state of Y depend on all inputs and states of X. The number of operations per input sample is initially 2081(We explain how the number of operations is calculated in a maximally fast approach [9] in Figure 3) Using the technique of [15] which unfolds the entire computation, the number can be reduced to 725 with an unfolding factor of 12. Our approach optimizes each subpart separately. This separate optimization is enabled from isolating the subparts using pipeline delays. The Figure 4 shows the resulting computation after the ....

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M. Srivastava, M. Potkonjak, "Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach," Design Automation Conference, pp. 343-348, 1996.

....all inputs and states of X. The number of operations per input sample is initially 2081 (We illustrate how the number of operations is calculated in a maximally fast procedure [7] using a simple linear computation with 2 states and 1 output which is described in Figure 2) Using the technique of [10] which unfolds the entire computation, the number can be reduced to 725 with an unfolding factor of 12. Our approach can optimize each subpart separately,which is enabled from isolating the subparts using pipeline delays. The Figure 3 shows the resulting computation after the isolation step. ....

....results in 522.27 operations. We perform subparts merging to further optimize. If the subparts C and D are merged and optimized together, the number of operations is further reduced to 399.4. The approach has reduced the number of operations by a factor of 1.82(5. 2) from the previous technique of [10] (from the initial number of operations) The main technical innovation of the research presented in this paper is the first approach for the minimization of the number of operations in general computations. The approach does not treat just significantly wide set of computations than the other ....

[Article contains additional citation context not shown here]

M. Srivastava, M. Potkonjak, "Power optimization in programmable processors and ASIC implementations of linear systems: transformationbased approach," Design Automation Conference, pp. 343-348, 1996.

....parallelism is traded for power reduction. The main technical innovation of the research is the first approach for minimizing the number of operations in general computations. The approach optimizes not only significantly wider set of computations than the other previously published techniques [11], but also outperforms or performs at least as well as other techniques on all examples. To the best of our knowledge this is the first optimization intensive approach for minimizing the number of operations in general computations. The second technical highlight is the quantitative analysis of ....

....[7] addressed the minimization of the number of multiplications and additions in linear computations in their maximally fast form so that the throughput is preserved. Sheliga and Sha [9] presented an approach to minimizing the number of operations in linear computations. Srivastava and Potkonjak [11] developed an approach to minimizing power for linear computations, based on the minimization of the number of operations. A variant of their technique is used in conquer phase of our approach. Our approach is different from theirs in two respects. First, their technique can handle only linear ....

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M. Srivastava and M. Potkonjak. Power optimization in programmable processors and ASIC implementations of linear systems: Transformation-based approach. Design Automation Conference, pages 343-- 348, 1996.

....Vol70, Sch84, Mes88, Par89, Fet90] The CAD treatment provides a necessary link to the application of the proposed approaches to the optimization of a variety of new tasks. For instance, it enables power reduction by a factor of about 25 times in many linear and feedback linear computations [Sri96]. 4.0 New Approach: Idea and Introductory Examples Probably the best way to introduce a basic idea is to use simple, yet non trivial examples. Figure 1 shows the control data flow graph (CDFG) of a 3 port serial adaptor which is regularly used in many ladder digital filter structures, such as ....

M. B. Srivastava, M. Potkonjak, "Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach", 1996 ACM/IEEE Design aUtomation Conference, to be published.

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