Stephan Gehring and Stefan Ludwig, "The Trianus System and Its Application to Custom Computing," th International Workshop on Field-Programmable Logic and Applications, Darmstadt, Germany, September 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....then the layout is changed to reflect that move. If a move is considered to be undesirable, then it is only accepted a small percentage of the time. Accepting a few bad moves helps to avoid any local minima in the placement space. Other algorithms exist that are not so based on random movements [Gehring96], although this searches a smaller 16 area of the placement space for a solution, and therefore may be unable to find a solution which meets performance requirements if a design uses a high percentage of the reconfigurable resources. Hard Soft Partition Structural Description Technology ....

....drawing or with a traditional waveform output. By examining these values, the operation of the circuit can be verified for correctness, and conflicts on individual wires can be seen. A number of simulation and debugging software systems have been developed which use some or all of these techniques [Arnold92, Bellows98, Gehring96, Hutchings99, Lysaght96, McKay99, Vasilko99]. 4.10 Software Summary Reconfigurable hardware systems require software compilation tools to allow programmers to harness the benefits of reconfigurable computing. On one end of the spectrum, circuits for reconfigurable systems can be designed manually, leveraging all application specific and ....

S. Gehring, S. Ludwig, "The Trianus System and Its Application to Custom Computing", Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein, M. Glesner, Eds. Berlin, Germany: SpringerVerlag, pp. 176-184, 1996. 33

....that is used in the OS4RC was modeled on an algorithm presented by Purna [15] there were a number of significant modifications made to it so it would work in a multiuser operating system for reconfigurable computing. Firstly, it has been interfaced to a fast deterministic placement algorithm [16, 17]. Secondly, an interaction between the partitioner and the placer is introduced so that the partitioner can be called iteratively to find the closest fit to the available area in a logic frame. Thirdly, it is now possible to specify the size of the partitions. Finally the new algorithm has ....

....space reserved for it, the logic modules have to be individually placed within that logic frame. Again, in the traditional design method the placement algorithm produces a high quality placement (minimize area and routing delays) but with no respect for run time. The placement algorithm chosen [16, 17] for the OS4RC trades an increase in fragmentation for a run time speed up. It is simple, but produces a fast constructive placement. Reasons why it was chosen were, the placement results yield a good chance of a quick successful route, the placement results are repeatable and the algorithm avoids ....

Gehring, S. and S. Ludwig. The Trianus System and its Application to Custom Computing. In 6th International Workshop on Field-Programmable Logic and Applications FPL'96. Darmstadt, Germany. Springer, September 1996

....engine was designed using the VHDL Elaborator [GraD98] and the Xilinx XACTstep Series 6000 Tools [Xili96] These tools were chosen based on availability and familiarity. Other tool suites for end to end development of XC6200 designs are available. The Oberon based Trianus system is one example [GehL96]. The interpolation engine was coded in structural VHDL with hardware specific attributes to guide the place and route tools during the creation of the physical design. The VHDL Elaborator produced an EDIF netlist of Xilinx Unified Library components from the VHDL code. The XACTstep Series 6000 ....

Stephan Gehring and Stefan Ludwig, "The Trianus System and Its Application to Custom Computing", 6 th International Workshop on Field-Programmable Logic and Applications, Darmstadt, Germany, September 1996.

....CAD tool that uses hierarchy and inheritance to describe user circuits. A Perle description, when compiled and executed, generates a netlist that is then processed by Xilinx place and route tools. Other similar examples of objectoriented circuit design languages include Spyder [4] and Lola [2]. Run time reconfiguration (RTR) has been receiving more attention lately and a few efforts are starting to report results with tools and run time environments. Luk and Shirazi [5] reported on compilation tools for RTR designs. Their tools consist of a partial evaluator, an incremental ....

S. Gehring and S. Ludwig. The trianus system and its application to custom computing. In R. W. Hartenstein and M. Glesner, editors, FieldProgrammable Logic: Smart Applications, New Paradigms, and Compilers. 6th International Workshop on Field-Programmable Logic and Applications, pages 176--184, Darmstadt, Germany, September 1996. Springer-Verlag.

....to meet current (e.g. instance specific, data dependent) computing requirements. Reconfigurable systems based on FPGAs have been used to construct custom computing machines with researchers investigating configurability [16, 31, 32, 33] ranging from embedded [35] or attached coprocessors [1, 15, 28, 43, 48] to the entire system [7, 8, 25, 26] Some recent approaches store multiple configurations onboard the device, enabling rapid hardware context switching [20, 35, 63, 64] Reconfigurable hardware has been designed for general purpose computing (e.g. DISC [72] NanoProcessor [74] PAM [69] ....

.... computations [52] genetic algorithms [29, 45] genome sequencing [70] image processing [5, 22, 57, 59, 73] signal processing [9, 17, 18, 27, 41, 51, 55, 58] and artificial neural networks [19, 24, 47] A number of development environments have been constructed, with the Trianus Lola system [28] being of particular interest. It provides designers access to dynamically reconfigurable hardware; however, the Lola language upon which it is based can only describe static circuits rather than dynamic processes [71] Researcher are discovering that better programming environments [3, 12, 13, ....

S. Gehring and S. Ludwig, The Trianus System and Its Application to Custom Computing, in Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, R. W. Hartstein and M. lesner, eds., Darmstadt, Germany, September 1995, Springer, pp. 176--184.

....the layout, then the layout is changed to reflect that move. If a move is considered to be undesirable, then it is only accepted a small percentage of the time. Accepting a few bad moves helps to avoid any local minima in the placement space. Placement can also be performed deterministically [Gehring96], although this searches a smaller area of the placement space for a solution, and therefore may be unable to find a solution which meets performance requirements if a design uses a high percentage of the reconfigurable resources. Finally, the different reconfigurable components comprising the ....

....be viewed either on a generated schematic drawing or with a traditional waveform output. By examining these values, the operation of the circuit can be verified for correctness, and conflicts on individual wires can be seen. Other simulation and debugging software systems have also been developed [Gehring96, Lysaght96, McKay99, Vasilko99]. Software Summary Reconfigurable hardware systems require software compilation tools to allow programmers to harness the benefits of reconfigurable computing. On one end of the spectrum, circuits for reconfigurable systems can be designed manually, leveraging all application specific and ....

S. Gehring, S. Ludwig, "The Trianus System and Its Application to Custom Computing", Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein, M. Glesner, Eds. Berlin, Germany: Springer-Verlag, pp. 176-184, 1996.

....that their productivity can be enhanced by reusable designs in the form of library elements, macros, modules or intellectual property cores. These components are developed carefully to ensure that they are efficient, validated and easy to use. Several development systems based on Java [1] Lola [2], C [3] ML [5] VHDL and Ruby [7] have been proposed. While the languages in these systems have their own goals and merits, none seems to meet al..l our requirements of: 1. having a simple syntax and semantics; 2. allowing a wide range of parameters in design descriptions; 3. providing support for ....

....circuits in similar technologies. Second, precise control over the placement of components is required to minimise reconfiguration time, since components at identical locations common to two successive configurations do not need to be reconfigured. A number of design languages, such as Lola [2], VHDL [7] and Lava [12] include mechanisms for specifying placement information. Pebble provides a facility similar to these languages. For example, a halfadder containing an xor2 gate beside an and2 gate can be described by the Pebble program in Fig. 5. BLOCK hadd (x,y:GENERIC) a,b:WIRE] ....

S. Gehring and S. Ludwig, "The Trianus system and its application to custom computing", in Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, LNCS 1142, Springer, 1996.

....4 FPGA Prototype The actual performance of CoMPARE can be better evaluated with a prototype. We have chosen the Xilinx XC6200 family for prototype implementation. The Trianus Hades CAD System developed at the Institute for Computer Systems (ETH Zurich, Switzerland) serves as design environment [12], the RTL and gate level description of the design were developed in Lola HDL. We described and synthesized every design unit of CoMPARE separately to ascertain the complexity in terms of XC6200 cells. Table 1 summarizes the results of the synthesis process. A complete CoMPARE prototype will fit ....

Gehring, S.W., Ludwig, S.: The Trianus System and its Application to Custom Computing, in Proceedings of FPL'96 (September 1996)

....which can either transfer configuration data from the RAM to the FPGAs, or save the complete processing state of the reconfigurable logic to RAM. Upwards of 11 million blocks per second can be configured in this way. Our primary design tool for the XC6216 is the Trianus integrated design system [2], running under the ETH Oberon operating system. With Trianus we have the option of generating designs in the Lola hardware description language [20] or placing blocks manually with a graphical editor. Further details can be found in [4] 4 Characterisation of suitable applications ....

S. Gehring and S. Ludwig "The Trianus System and its Application to Custom Computing", In Proc. 6th International Workshop on FieldProgrammable Logic and Applications , September 1996.

....and could thus profitably be reused by several tools. Taking advantage of this reduces the size and memory requirements of tools and eases system maintenance. We have addressed these problems by capturing the common traits of design tools in an application framework for circuit design tools [9, 8]. To create tools for a specific FPGA architecture, this architecture independent framework is extended with architecturespecific components. The foundation for the tight integration of the framework and its extensions lies in the use of a single data structure to represent circuits throughout the ....

....tools for a specific FPGA architecture, this architecture independent framework is extended with architecturespecific components. The foundation for the tight integration of the framework and its extensions lies in the use of a single data structure to represent circuits throughout the system [9, 8]. That is, all tools, whether architecture independent or dependent, use a universal circuit representation defined in the core of the framework (Figure 1) The design tools operate in a shared memory environment and modify the data structure in situ. Data exchange between tools can thus be ....

S. Gehring, S. Ludwig. The Trianus System and its Application to Custom Computing.Proc. 6th Intl. Workshop on Field-Programmable Logic and Applications. LNCS 1142, Springer, 1996.

....read again, i.e. the data structures representing the design in the first tool are externalized to disk and subsequently internalized and translated to the data structures needed by the second tool. 3. 1 Trianus Framework To remedy the aforementioned problems, the Trianus framework was developed [GL96, Geh97]. Trianus is an extensible framework of tightly integrated FPGA architectureindependent tools (front end) which are supplemented with architecture dependent tools for specific FPGA architectures (back ends) Together they form complete circuit development systems from initial design entry to ....

....by the editor framework. The hierarchical data structure encourages the use of hierarchical information for design representation. Data Structure HDL Schema Layout Extract Place Route Extract Compile Place Route Extract Fig. 2. Trianus Tools 3. 2 Hades Synthesis Back End The Hades software [GL96, Lud97] implements a Trianus back end and comprises a technology mapper, a placer, a router, a bitstream generator and a runtime system. The Hades hardware is a reconfigurable coprocessor based on the XC6200 FPGA from Xilinx and is described in [Lud96, Lud97] The technology mapper is concerned with the ....

S Gehring, S Ludwig. "The Trianus System and its Application to Custom Computing", Proc. 6th Intl. Workshop on FieldProgrammable Logic and Applications. LNCS 1142, Springer, 1996.

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Stephan Gehring and Stefan Ludwig, "The Trianus System and Its Application to Custom Computing," th International Workshop on Field-Programmable Logic and Applications, Darmstadt, Germany, September 1996.

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Gehring, S. and Ludwig, S. The Trianus system and its application to custom computing. In Proceedings 6 International Workshop on Field Programmable Logic and Applications, pp. 176 -- 184, September 1996.

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