D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... between data and locks, then check that the program holds the lock whenever it accesses the corresponding data [94, 28] Other analyses trace the control transfers associated with the use of synchronization constructs such as the post and wait constructs used in parallel dialects of Fortran [71, 18, 36, 17], the Ada rendezvous constructs [95, 99, 33, 70, 35] or the Java wait and notify constructs [73, 74] The goal is to determine that the synchronization actions temporally separate conflicting accesses to shared data. In some cases it may be important to recognize that parallel tasks access ....

....of tasks that may not execute concurrently, then remove edges between these regions. The characteristics of the analysis depend on the specific synchronization constructs. Researchers have developed algorithms for programs that use the post and wait constructs used in parallel dialects of Fortran [18, 36, 17], for the Ada rendezvous constructs [95, 33, 70, 35] and for the Java wait and notify constructs [73, 74] The basic idea behind these algorithms is to match each blocking action (such as a wait or accept) with its potential corresponding trigger actions (such as post or notify) from other ....

D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, Madison, WI, May 1988. 15

....to the diculty in reproducing the erroneous behavior. Analysis techniques for concurrent programs may be broadly classi ed into : Static analysis : These techniques do not require program execution and perform compile time analysis for critical program properties. These include data ow analysis [10], reachability analysis [31] and formal veri cation [23] Dynamic analysis : These techniques require program execution and correspond to run time debugging of the program behavior. These range from simple extensions of sequential techniques [4] to complex techniques that rely on monitoring the ....

D. Callahan and J. Subhlok. Static analysis of low level synchronization. Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, published in ACM SIGPLAN NOTICES, 24(1):100-112, Jan 1989.

....Directions 10.1 Related Work Analysis of parallel programs for detecting races has been a very popular research topic. Data flow analysis of these programs for compile time optimizations has become a topic of interest only recently. To our knowledge, none of the earlier work on race detection [19, 20, 21, 22] uses the SSA form of a program. We have shown that an outcome of translating explicitly parallel programs to their SSA form is static detection of write write races in these programs . However, race detection is not the main focus of this research work. More recently there has been considerable ....

D. Callahan and J. Subhlok. Static Analysis of low-level synchronization. In Proc. of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, Madison, WA, May 1988.

....even more difficult when we consider analyzing programs with branching (but without loops) For each input, the program with branching can be viewed as a set of branch free programs. Each legal combination of branch choices for that input leads to one branch free program. A simplifying assumption [CS88] is that all branch combinations are possible, so that any set of branch choices is legal. Without this assumption it is NP hard to determine which branch choices are legal (see Theorem 2) Each branch free program associated with a branching program input pair has its own set of races between ....

.... ffl post wait no clear is in P [NG92] Nonmono tonic ffl single semaphore is in P [LKN93] ffl post wait clear is NP hard (Thm: 1) ffl semaphores are co NP hard[NM90] semaphores [HMW93] No loops Monotonic ffl fork join is NP hard (Thm: 2) ffl post wait no clear is Co NPhard [CS88] even if all paths are executable, fork join [MC91, DS90, NR88] post wait no clear [CKS90] Nonmono tonic ffl post wait clear is NP hard (Thm: 1 or [CS88] ffl semaphores are NP hard fork join [MC91, DS90, NR88] post wait no clear [CKS90] Unrestricted any Undecidable (Thm: 3) ....

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D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In Proc. Workshop on Parallel and Distributed Debugging, pages 100--111, May 1988.

....Phred system provides such determinacy information to the programmer. Various source analysis techniques have been developed for finding nondeterminacies in parallel programs. Taylor s static analysis techniques for Ada programs can be found in [24] Techniques developed by Callahan and Subhlok [10] improve on those of Taylor by eliminating potentially exponential behavior. In [14] Emrath and Padua classify various kinds of nondeterminacy and present source analysis techniques for detecting nondeterminacies. The issue of determinacy can also addressed from the standpoint of debugging ....

D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, Madison,WA, May 1988. Available as Rice University, Dept. of Computer Science Technical Report TR88-70.

....the MHP algorithm turned out to be less than ideally precise, the number of spurious pairs was small compared to the total number of ideal MHP pairs. Several approaches for computing MHP information for programs using various synchronization mechanisms have been suggested. Callahan and Subhlok [4] proposed a data flow algorithm that computes, for each statement in a concurrent program with post wait synchronization, the set of statements that must be executed before this statement can be executed (B4 analysis) Duesterwald and Soffa [6] applied this approach to the Ada rendezvous model and ....

D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, number 1, pages 100--111, Jan. 1989.

....and McDowell [9] and McDowell [19] include data values in the concurrency states, and discuss a number of techniques for reducing the number of nodes. A different approach is to determine which statements are executed before others, based on the synchronization statements. Callahan and Subhlok [2] and Callahan, Kennedy and Subhlok [3] compute an approximation of this relation and extend it with dependence distance information for loops. Masticola and Ryder [18] employ this information, along with other techniques, to compute a can t happen together relation for statements. As mentioned ....

D. Callahan and J. Subhlok. Static Analysis of Low-Level Synchronization. In Proceedings of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, Madison, WI USA,

....Races exist between these pairs of blocks since the program imposes no orderings between them. There is no race between b6 and b10, since they are ordered by synchronization in the program (the join at the end 69 of b6 ) Three basic approaches have been used to detect races. Static techniques [4, 9, 16, 27, 62] examine the text of a program and use static analysis to approximate the shared memory locations accessed by each code block. This information, combined with the concurrency information in the POEG, detects apparent races by finding pairs of unordered blocks making conflicting accesses to common ....

David Callahan and Jaspal Subhlok. Static Analysis of Low-Level Synchronization. Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel 116 and Distributed Debugging, published in ACM SIGPLAN Notices, 24(1):100-- 111, January 1989.

....to static analysis are generally used. In the first approach, all possible states that the program can exist in are traversed and a graph of the state space is constructed either explicitly [15] or implicitly. In the second approach, dataflow analysis is used to detect potential event orderings [2, 5]. In general, dataflow methods are less accurate, but have better time and space complexity than state space methods. Static analysis is used to augment dynamic analysis [1, 6, 7, 8, 9, 14, 22] Dynamic analysis detects races for a particular execution of the program; these methods generally ....

Callahan D. and J. Subhlok, "Static Analysis of Low-Level Synchronization," Proc. SIGPLAN Workshop on Parallel and Distributed Debugging, pp. 100-111, May. 1988.

....analyze the synchronization accesses in the program to obtain precedence and mutual exclusion information. Others have proposed algorithms for analyzing synchronization constructs in the context of framing data flow equations for parallel programs, where strict precedence information is necessary [5][9] Our algorithm for analyzing post wait synchronization is similar in spirit; however, we can also exploit mutual exclusion information on accesses. Also related to our work is the research that proposes weaker memory models [1, 8] Those approaches change the programmer s model by giving ....

D. Callahan and J. Subhlok. Static Analysis of Low-level Synchronization. In ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, May 1988.

....We repeat Equation (10) here: Accept (D; y) 0 Scope(D[t y ] y) 0 SigN set (D; y) 3. All head nodes may execute at the same time. a) The nodes in D must represent statements whose instances can happen together. b) All nodes in D are co executable in the sense of Callahan and Subhlok [CS88]. In the presence of accept do statements, we have new information on co executability of the nodes in D. It must be possible to have enough ENGAGED nodes of each signal type on the execution wave to drive the nodes in D to their scope depth with respect to all signal types. This implies Equation ....

....(10) as follows: 8y such that UngSis (D; y) 0 Scope(D[t y ] y) 0 SigN set (D; y) 3. All head nodes may execute at the same time. a) The nodes in D must represent statements whose instances can happen together. b) All nodes in D are co executable in the sense of Callahan and Subhlok [CS88]. This implies Equation (7) X y2Sigs [Scope set (D; y) 0 SigN set (D; y) jEj 0 jDj) 4. The nodes of D must be able to execute concurrently with some set of remaining nodes E0D such that none of the nodes in E 0D can rendezvous with each other or with any member of D. If any node a i of ....

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Callahan, D. and Subhlok, J. "Static analysis of low-level synchronization." SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, 1988, 100-111.

....[MiC89] Net93] They make cyclical debugging possible, but often ignore individual parts of a cycle. Static analysis extracts more information from P when probe effect [Sto88] a principle similar to Hiesenberg s uncertainty principle, limits further instrumentation [Tay83] TaO80] BBC88] [CaS89], McD89] They analyze P and are limited to the P M part of the debugging cycle. 2.2 Problems in Various Parts of the Cycle Fig. 2 2 shows the problems and ambiguities often encountered during the mapping between different representations in various parts of the debugging cycle. Static Probe ....

....PPL, and so on. Its equivalent in distributed systems is the send( of a message. From a text containing blocking synchronization, signal synchronization and non synchronization statements, static analysis techniques routinely extract a synchronization control flow graph [Tay83] TO80] BBC88] [CaS89], McD89] MiC89] The graph typically contains three types of nodes and two types of arcs. Nodes represent blocking synchronization, signal synchronization, and control decision statements. While arcs represent interprocess synchronization dependences and intra process control flow dependences. ....

David Callahan and Jaspal Subhlok, "Static Analysis of Low-level Synchronization," Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, ACM SIGPLAN Notices, 24(1), pp. 100--111, January 1989. 148

....PVM library to make use of the Xmdb facility. When debugging is done, the user program then is re linked to the PVM library to actually execute in PVM environment. DamodaranKamal and Francioni cited three strategies for detecting non determinism in their work [4] compile time analysis (example:[1]) which is done before the program execution and is independent of input data, postmortem trace analysis (example: 9] which analyzes program trace after execution using various software techniques, and onthe fly mechanism (example: 10, 14] which makes decision about what to trace and record ....

D. Callahan and J. Sublok, "Static Analysis of Low Level Synchronization", Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging, May 1988

....Analyzing synchronization in this context is similar to analyzing the synchronization between the two branches in the [If Multi] case, for which we only allow very simple synchronization sequences. None of the many papers on this subject present exact solutions for more general situations [2, 3, 9, 18, 19, 22, 26]. 7 Conclusion We have identified an important property of SPMD programs that current languages do not explicitly support: The portion of control and data flow governing global synchronization that is identical across all processes. This synchronization kernel structures the entire application. ....

D. Callahan and J. Subhlok. Static Analysis of LowLevel Synchronization. In Proceedings of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, Madison, WI USA, [1] 1989. ACM Press , New York, NY , USA. Published as SIGPLAN Notices, volume 24, number 1.

....the next section, we extend these data flow equations to consider event synchronization between parallel Sections. 6 Including the effect of Synchronization We extend the data flow equations in the previous section to consider event synchronization by using the preserved sets formulation given in [3]. Synchronization using post wait occurs between different threads that execute in parallel. Synchronization edges carry data flow information, i.e. they propagate values of variables from the thread that posted the event to the thread that is waiting for the event to be posted. According to [9] ....

....It is also possible that these multiple posts and waits are executed conditionally. Thus, a synchronization edge does not always imply an execution order. We are, however, interested in the potential execution order for computing the reaching definition information. Preserved sets, as defined in [3] give precisely the set of nodes that execute before a given node, defined as follows: Definition 1 A node n j 2 Preserved(n i ) if and only if for all parallel executions x, if n j and n i are both executed, n j is completed before n i is begun. However, Callahan and Subhlok [3] have shown ....

[Article contains additional citation context not shown here]

D. Callahan and J. Subhlok. Static Analysis of low-level synchronization. In Proc. of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, Madison, WA, May 1988.

....by suitable analysis techniques (such as reaching decompositions analysis [19] Such information can be used by optimizations that redistribute the data and computation, and to bind the XDP communication primitives to efficient object code. Finally, analysis of the parallel execution order [9, 8, 13, 14, 15] can yield more precise information about which communications statements can be reordered without introducing deadlock or other errors. This information can be represented by removing some of the uses of state variables at certain occurrences of synchronization intrinsics. 5.2 Optimization In ....

D. Callahan and J. Subhlok. Static analysis of low-level synchronization. Workshop on Parallel and Distributed Debugging, pages 100--111, May 1988.

....[Section 4.2] 3. Place functions ( assignments) Section 4.3] 4.1 Partial ordering of conflicting statements In order to get information about the effect of interleaving among statements in different threads, we need to get the partial ordering of the statements. Callahan and Subhlok[4] used data flow analysis to get an event ordering for explicitly parallel programs without loops. We use a data flow analysis framework similar to theirs. This is essentially the same as the common ancestor algorithm by Emrath, Ghosh and Padua [6, 7] This method computes an conservative ....

David Callahan and Jaspal Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, May 1988.

....errors, are probably the most insidious class of bugs in parallel programs. Due to the infamous probe effect [16] these bugs are difficult to detect using debuggers that alter the execution of a program, so static analysis would seem to be a perfect approach. Unfortunately, as pointed out in [10], this analysis is computationally expensive and is not generally applicable to all parallel programs. Furthermore, since it is a static technique, it does not mesh well with the interactive nature of the Id development environment. 3.2 Inadequate Control Flow Debuggers In the description of ....

....vadd) Alternatively, we could stop the program when A, the first argument to vadd, is computed by specifying (bind vadd A) Using connectors, we can specify very complicated but useful conditions. Suppose we wanted to stop the program if the bounds of A were not within a certain range, such as [1,10]. We could use the following halt condition to achieve this (any ( bind vadd l) 1) bind vadd u) 10) This halt condition indicates that the program should be halted if the variable l, the lower bound of the vector, is bound to a value less than 1, or if the variable u, the upper bound of ....

D. Callahan and J. Subhlok. Static Analysis of Low-level Synchronization. In Proceedings of the Workshop on Parallel and Distributed Debugging, pages 100--111. ACM, January 1988.

....[Section 5.2. 3. Place functions ( assignments) Section 5.3. 5.1. Partial ordering of conflicting statements In order to get the information of the interleaving among statements in different thread, we need to get the partial ordering of the statements. Callahan and Subhlok[3] used data flow analysis to get an event ordering for explicitly parallel programs without loops. We use a data flow analysis framework similar to theirs. Essentially this is the same as the method so called common ancestor algorithm by Emrath, Ghosh and Padua [7, 5, 6] This method computes an ....

David Callahan and Jaspal Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, May 1988.

No context found.

D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, 1988.

No context found.

D. Callahan and J. Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN and SIGOPS Workshop on Parallel and Distributed Debugging, Madison, WI, May 1988. 15

No context found.

David Callahan and Jaspal Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, pages 100--111, May 1988.

No context found.

D. Callahan and J. Sublok, "Static Analysis of Low Level Synchronization", Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging, May 1988

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David Callahan and Jaspal Subhlok. Static analysis of low-level synchronization. In Proceedings of the ACM SIGPLAN/SIGOPS Workshop on Parallel and Distributed Debugging, pages 100{ 111, May 1988.

No context found.

D. Callahan and J. Subhlok, "Static Analysis of Low-Level Synchronizations," ACM SIGPLAN Notices, 24(1), (Jan `89)

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