K. C. Yeager, "The MIPS R10000 superscalar microprocessor," in Proc. Int. Symp. Microarchitecture, Apr. 1996, pp. 28--40. Home/Search Document Not in Database Summary Related Articles Check |
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A High-Bandwidth Memory Pipeline for Wide Issue Processors - Cho, Yew, Lee (2001) (1 citation) (Correct)
....instruction level parallelism, runtime stack, data stream partitioning, multiported data cache. I INTRODUCTION ECHNOLOGICAL and architectural innovations have en abled development of powerful microprocessors that can execute several instructions concurrently at a very high clock rate [11] [36], 12] These processors select and execute independent instructions at runtime, assisted by hardware mechanisms for control speculation, register renaming, and data flow execution [15] With ample onchip hardware resources that will become available within a few years, researchers are actively ....
....dual ports. For example, Alpha 21264 provides a two ported data cache by doubling the cache access rate compared with the normal processor clock [12] Alpha 21164, the predecessor of the 21264, uses a replicated data cache [8] and the MIPS R10000 implements a two way interleaved data cache [36]. Each design, however, is either costly to implement, and or can have significant drawbacks. The time division multiplexing does not scale beyond a certain number of 1. Reportedly, dual ported synchronous SRAMs are up to around 50 percent slower, nearly 150 percent larger, and or consume over 120 ....
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K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor," IEEE Micro, vol. 16, no. 2, pp. 28-40, Apr. 1996.
Improving Processor Performance by Simplifying and Bypassing.. - Yi, Lilja (2002) (3 citations) (Correct)
....and Models Table 3 shows the base processor configuration used in this study while Table 4 shows the instruction execution latencies. The values shown in both tables are representative of the values that are used in commercially available processors such as the Alpha 21264 and the MIPS R10000 [Kessler98, Yeager96]. Parameters Final Values # of Integer ALUs 2 # of FP ALUs 2 # of Integer Multipliers Dividers 1 # of Floating Point Multipliers Dividers 1 # of Instruction Fetch Queue Entries 32 Decode, Issue, Commit Width 4 Way # of Reorder Buffer Entries 64 # of Load Store Queue Entries 32 # of ....
K. Yeager; "The MIPS R10000 Superscalar Microprocessor"; IEEE Micro, Vol. 16, No. 2, March-April 1996; Pages 28-40.
Improving Processor Performance by Simplifying and Bypassing.. - Yi, Lilja (2002) (3 citations) (Correct)
....4 way associativity, and a 12 cycle hit latency. The memory latency of the first block was 60 cycles while each following block took 5 cycles. The branch predictor was a combined predictor with 8K entries. These parameter values are similar to those found in the Alpha 21264 [3] and the MIPS R10000 [10]. 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 0 0 ADD SUB MULT DIV AND OR XOR SLL SRL SRA FADD FSUB FMUL FDIV FABS FSQRT Total I n t r u o n T y p Percent Trivial Per Instruction Type S P E C M e d a b e n h Figure 2. Speedup due to trivial computation bypass simplification for the ....
K. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, Vol. 16, No. 2, MarchApril 1996, Pages 28-40.
A Statistically Rigorous Approach for Improving Simulation.. - Joshua Yi David (2002) (1 citation) (Correct)
....commercial processors. Our list of commercial processors included the Alpha 21164 [Bannon97, Edmondson95] and 21264 [Kessler98, Kessler99, Leiholz97, Matson98] the UltraSparc I [Tremblay96] II [Normoyle98] and III [Horel99] HP PA 8000 [Kumar97] the PowerPC 604 [Song94] and the MIPS R10000 [Yeager96]. To fill in the gaps left by the aforementioned papers, Silc99, Sima97] and several web searches were also used as references. Based on the range of reasonable values, we chose a low and high value for each parameter. Tables 6, 7, and 8 show the final values for each of the relevant parameters ....
K. Yeager; "The MIPS R10000 Superscalar Microprocessor"; IEEE Micro, Vol. 16, No. 2, March-April 1996; Pages 28-40.
A Statistically Rigorous Approach for Improving Simulation.. - Yi, Lilja, Hawkins (2002) (1 citation) (Correct)
....D TLB Latency Same as I TLB Latency values on those found in several commercial processors. Our list of commercial processors included the Alpha 21164 [1, 6] and 21264 [12, 13, 16, 18] the UltraSparc I [29] II [21] and III [11] the HP PA 8000 [15] the PowerPC 604 [28] and the MIPS R10000 [30]. To fill in the gaps left by these papers, 24, 25] and several web searches were also used as references. Tables 3, 4, and 5 show the final values for each of the relevant parameters in the processor core, the functional units, and the memory hierarchy, respectively. A couple of parameters ....
K. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, Vol. 16, No. 2, March-April 1996, Pages 28-40.
Dynamic Speedup Calculation through Self-Analysis - Corbalán, Labarta (1999) (1 citation) (Correct)
....the hardware counters provided by the architecture, and by instrumenting the parallel library. However, one of the major limitations of this method to calculate the efficiency is that it is closely dependent on the architecture. In some current multiprocessors systems, such as the Origin 2000[15][6] the stall time cannot be measured, since the corresponding hardware counter is not provided by the architecture. On the other hand, there are some features of the system that do have influence on the speedup, and that are not totally taken into account in the previous equation. One of the ....
K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor" . IEEE Micro vol. 16, 2 pp 28-40.
Reservation Station Architecture for Mutable.. - Solihin, Cameron, .. (1999) (Correct)
....realization of a mutable functional unit is within an embedded reconfigurable fabric using Field Programmable Gate Array (FPGA) technology. Such a technique has been proposed as a mechanism for creating application specific hardware circuits to augment the capability of a conventional processor [6,7,11,14,15,21]. To take advantage of the reconfigurable fabric, the compiler must: Identify portions of code that can be accelerated within the reconfigurable fabric; Synthesize hardware circuits to realize those code fragments; Generate code to transfer state between the processor and reconfigurable ....
Kenneth C. Yeager, "The MIPS R10000 Superscalar Microprocessor", Proceedings of the 27 th Annual International Symposium on Microarchitecture, pp. 28-40, 1996.
Speculative Locks for Concurrent Execution of Critical.. - Martinez, Torrellas (2001) (4 citations) (Correct)
....a spin locking loop. To give a concrete example, we will assume that the SCU uses T T S. Meanwhile, the processor checkpoints its internal state and then continues execution past the acquire point. State checkpointing is a feature already present in existing processors, such as the MIPS R10000 [23]. Memory accesses by the processor past the acquire point are deemed speculative by the SCU if the Owner bit is not set. Handling of the Lock The SCU remembers the speculative accesses by setting the Speculative bit of the cache lines accessed in speculative mode by the local thread. Aside from ....
K. Yeager. "The MIPS R10000 Superscalar Microprocessor". IEEE Micro, Vol. 6, No. 2, April 1996.
An Adaptive Issue Queue for Reduced Power at High.. - Alper Buyuktosunoglu.. (2000) (19 citations) (Correct)
.... the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design) 1 Introduction The out of order issue queue structure is a major contributor to the overall power consumption in a modern superscalar processor, like the Alpha 21264 and Mips R10000 [1, 2]. It also requires the use of complex control logic in determining and selecting the ready instructions. Such complexity, besides adding to the overall power consumption, also complicates the verification task. Recent work by Gonzalez et al. 3, 4] has addressed these problems, by proposing design ....
....An instruction is ready to issue when the data needed by its source operands and the functional unit are available or will be available by the time the instruction is ready to read the operands, prior to execution. Many superscalar microprocessors, such as the Alpha 21264 [1] and Mips R10000 [2] use a distributed issue queue structure, which may include separate queues for integer and floating point operations. For instance in the Alpha 21264 [9] the issue queue is implemented as flip flop latch based FIFO queues with a compaction strategy, i.e. every cycle, the instructions in the ....
K.Yeager, "The Mips R10000 superscalar microprocessor," IEEE Micro, 16(2): 28-41, April 1996.
Performance-Driven Processor Allocation - Corbalán, Martorell, Labarta (2000) (Correct)
....variables that define the application adaptability have been set to the following values 5 : MP BLOCKTIME=200000 and OMP DYNAMIC=TRUE. 5.1 Architecture, applications and workloads All the workloads have been executed in an Origin2000 [13] 29] with 64 processors. Each processor is a MIPS R10000 [33] at 250 MHZ, with two separated instruction and data L1 cache (32 Kbytes) and a secondary unified instruction data cache (4 Mbytes) 4. Specified as a command line parameter of the application or setting an environment variable 5. These values have been tuned empirically to perform well under ....
K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor" . IEEE Micro vol. 16, 2 pp 28-40
Execution Cache-Based Microarchitecture for Power-Efficient .. - Talpes, Marculescu (2005) (Correct)
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K. C. Yeager, "The MIPS R10000 superscalar microprocessor," in Proc. Int. Symp. Microarchitecture, Apr. 1996, pp. 28--40.
Implementation Issues in Modern Cache Memory - Peir, Hsu, Smith (1998) (Correct)
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K. Yeager, "The MIPS R10000 Superscalar Microprocessor," IEEE Micro, Vol. 16(2), April 1996.
Journal of Instruction-Level Parallelism 6 (2004) 1-23.. - Ai Access Foundation (2004) (Correct)
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K. C. Yeager. "The MIPS R10000 superscalar microprocessor." IEEE Micro, 16(2):28--40, April 1996.
Improving Processor Performance and Simulation Methodology - Yi (Correct)
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K. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, Vol. 16, No. 2, March-April 1996, Pages 28-40.
Visualizing Application Behavior on Superscalar Processors - Chris Stolte Robert (1999) (1 citation) (Correct)
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Kenneth Yeager. "The MIPS R10000 Superscalar Microprocessor. " IEEE Micro, 16(2):28-40, April 1996.
Area and System Clock Effects on SMT/CMP Processors - James Burns Jean-Luc (2000) (2 citations) (Correct)
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K.C. Yeager, "The MIPS R10000 superscalar microprocessor", IEEE Micro, April 1996.
Improving Processor Performance and Simulation Methodology - Yi (2003) (Correct)
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K. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, Vol. 16, No. 2, March-April 1996, Pages 28-40.
Dynamic Performance Analysis: - Selfanalyzer Julita Corbalan (2002) (Correct)
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K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor". IEEE Micro vol. 16, 2 pp. 28-40, 1996.
Three Extensions to Register Integration - Roth, Al. (2002) (1 citation) (Correct)
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K. Yeager. "The MIPS R10000 Superscalar Microprocessor." IEEE Micro, Apr. 1996.
Improving Gang Scheduling through - Job Performance Analysis (2001) (Correct)
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K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor". IEEE Micro vol. 16, 2 pp. 28-40, 1996.
Address Prediction and Recovery Mechanisms - Llena (2002) (Correct)
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K.C. Yeager. (1996). The MIPS R10000 Superscalar Microprocessor. IEEE MICRO, Vol. 16(2), pp 28-41.
Constraint Graph Analysis of Multithreaded Programs - Cain, al. (2004) (Correct)
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K. C. Yeager. "The MIPS R10000 superscalar microprocessor." IEEE Micro, 16(2):28--40, April 1996.
Mixed-Clock Issue Queue Design for Energy Aware.. - Rapaka, Talpes.. (Correct)
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K. C. Yeager, "The Mips R10000 superscalar microprocessor," in IEEE Micro, vol. 16, pp. 28-41, Apr 1996.
Improving Power Efficiency with an Asymmetric.. - Hu, Kaxiras, Martonosi (Correct)
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Yeager, K. (1996) The MIPS R10000 Superscalar Microprocessor. In: IEEE Micro (16)2: pp. 28--40
Improving Gang Scheduling through - Job Performance Analysis (Correct)
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K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor ". IEEE Micro vol. 16, 2, pp. 28-40, 1996.
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