M. Peiron, M. Valero, E. Ayguade, and T. Lang. Vector multiprocessors with arbitrated memory access. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....determine when precharge cycles may be skipped [16] Valero et al. propose efficient hardware to dynamically avoid bank conflicts in vector processors by accessing vector elements out of order. They analyze this system first for single vectors [18] and then extend the work for multiple vectors [15]. del Corral and Llaberia analyze a related hardware scheme for avoiding bank conflicts among multiple vectors in complex memory systems [8] These access scheduling schemes focus on memory systems composed of SRAM components (with uniform access time) and thus they do not address precharge ....

M. Peiron, M. Valero, E. Ayguade, and T. Lang. Vector multiprocessors with arbitrated memory access. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.

....in the case that the request rate was greater than the service rate the concurrent access did not reach a synchronized situation. We propose a new algorithm that dynamically determines which request gains the access. Dynamical arbitrations are used in the CRAY X MP and Y MP [8] Other proposals, [5] and [12] use synchronous arbitration algorithms, the adjudication does not depend on the request, it is pre established, and memory references must be generated in function of the algorithm. The proposed arbitration is performed at the level of the memory modules, and is a combination of two ....

M. Peiron, M. Valero, E. Ayguade and T. Lang, Vector Multiprocessors with Arbitrated Memory Access, Proc. Int. Symp. Computer Architecture, 1995, pp. 243-252.

....row address. 2. CAS 0 , initial column address. 3. Deltak, burst stride. 4. DAT, number of data items contained in the bank. We have developed an algorithm that takes as input a command and a bank index and generates the appropriate subcommand. This algorithm develops the ideas contained in [12] assuming low order interleaving. A full description of this algorithm is beyond the scope of this paper and can be found in [13] From the point of view of the results presented in this paper, the most important characteristic of the algorithm is its computational cost, which depends on the ....

Montse Peiron, Mateo Valero, Eduard Aygaud'e, and Tom'as Lang. Vector multiprocessors with arbitrated memory access. In ISCA-22, pages 243--252, Santa Margherita Ligure, Italy, June 22--24, 1995.

....A third advantage is related to the way the memory system is accessed: a single vector instruction can exactly specify a long sequence of memory addresses. Consequently, the hardware has considerable advance knowledge regarding memory references, can schedule these accesses in an efficient way [4], and needs to access no more data than is actually needed. In addition, a vector memory operation is able to amortize start up latencies over a potentially long stream of vector elements. The goal of this paper is to show that, merging the ILP and DLP concepts, we can exploit the advantages of ....

M. Peiron, M. Valero, E. Ayguade and T. Lang. "Vector Multiprocessors with Arbitrated Memory Access". In 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligura, Italy, June 22-24, 1995, pp. 243-252.

....On the contrary, vectors have inherent advantages when it comes to memory usage. A single instruction can exactly specify a long sequence of memory addresses. Consequently, the hardware has considerable advance knowledge regarding memory references, can schedule these accesses in an efficient way [11], and needs to access no more data than is actually needed. In addition, a vector memory operation is able to amortize startup latencies over a potentially long stream of vector elements. Recent studies [5, 7] have shown that by using some ILP techniques coupled with a DLP engine, up to 100 cycles ....

M. Peiron, M. Valero, E. Ayguad'e, and T. Lang. Vector multiprocessors with arbitrated memory access. In 22nd Annual International Symposium on Computer Architecture, pages 243--252, Santa Margherita Ligure, Italy, June 22--24, 1995.

....way. A third advantage is related to the way the memory system is accessed: a single vector instruction can exactly specify a long sequence of memory addresses. Consequently, the hardware has considerable advance knowledge regarding memory references, can schedule these accesses in an efficient way[8], and needs to access no more data than is actually needed. In addition, a vector memory operation is able to amortize start up latencies over a potentially long stream of vector elements. In this paper we make a comparison between vector and superscalar processors by analysing the behaviour of a ....

M. Peiron, M. Valero, E. Ayguade and T. Lang. "Vector Multiprocessors with Arbitrated Memory Access". In 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligura, Italy, June 22-24, 1995, pp. 243-252.

....A third advantage is related to the way the memory system is accessed: a single vector instruction can exactly specify a long sequence of memory addresses. Consequently, the hardware has considerable advance knowledge regarding memory references, can schedule these accesses in an efficient way [4], and needs to access no more data than is actually needed. In addition, a vector memory operation is able to amortize start up latencies over a potentially long stream of vector elements. The goal of this paper is to show that, merging the ILP and DLP concepts, we can exploit the advantages of ....

M. Peiron, M. Valero, E. Ayguade and T. Lang. "Vector Multiprocessors with Arbitrated Memory Access". In 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligura, Italy, June 22-24, 1995, pp. 243-252.

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M. Peiron, M. Valero, E. Ayguade, and T. Lang. Vector multiprocessors with arbitrated memory access. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.

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PEIRON, M., VALERO, M., AYGUADE, E., AND LANG, T. Vector multiprocessors with arbitrated memory access. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (June 1995), pp. 243--252.

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