K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single Chip Multiprocessor. Proceedings of ASPLOS'1996. Home/Search Document Not in Database Summary Related Articles Check |
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Memory System Behavior of Java-Based Middleware - Karlsson, al. (2003) (6 citations) (Correct)
....footprint on an absolute, not just a percentage, basis. 5.3. Shared Caches The high cache to cache transfer rates of these workloads suggest that they might benefit from a shared cache memory system, which have become increasingly common with the emergence of chip multiprocessors (CMPs) [14]. Shared caches have two benefits. First, they eliminate coherence misses between the processors sharing the same cache (private L1 caches will still cause coherence misses, but these can be satisfied on chip much faster than conventional off chip coherence misses) Second, compulsory misses may ....
....a major performance issue. Although we did not specifically measure TLB miss rates, we found that using the intimate shared memory (ISM) feature of Solaris, which increases the page size from 8 KB to 4 MB, increased performance of ECperf by more than 10 . Barroso, et al. 4] and Olukotun, et al. [14] discuss the performance benefits of chip multiprocessors using shared caches. We extend their work by evaluating the impact of shared caches on SPECjbb and ECperf. 7. Conclusions In this paper, we have presented a detailed characterization of two popular Java based middleware benchmarks. ECperf ....
Kunle Olukotun, Basem A. Nayfeh, L. Hammond, K. Wilson, and K.-Y. Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.
WaveScalar - Swanson, Michelson, Oskin (2003) (Correct)
....the two is whether resources are partitioned statically between the threads or shared dynamically. In the WaveCache this is simply a parameter to the WaveCache replacement policy: for the SMT [70] model, all the threads compete for the available processing elements; in the chip multiprocessor [71] model the WaveCache confines each thread to a portion of the grid. By simply adding a THREAD ID to each wave number, and modifying the memory interface accordingly, a vast array of multithreading strategies become possible. 7 Conclusion In this paper we have presented WaveScalar, a new ....
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The case for a single-chip multiprocessor," in Proceedings of the 8th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IIV), 1996. 23
An Integer Linear Programming Based Approach for.. - Kadayif, Kandemir, Sezer (2002) (3 citations) (Correct)
....cores in a single chip. This strategy has advantages over an alternate strategy which puts a more powerful and complex processor in the chip. First, the design of an on chip multiprocessor composed of multiple simple processor cores is simpler than that of a complex single processor system [8, 13]. Note that this simplicity also helps reduce the time spent in verification and validation [12] Second, an on chip multiprocessor is expected to result in better utilization of the silicon space. The extra logic that would be spent on register renaming, instruction wake up, and register bypass ....
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single chip multiprocessor. In Proc. the 7th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1996, pp. 2--11.
An Analysis of Software Interface Issues for SMT Processors - Redstone (2002) (1 citation) (Correct)
....operating system as different microarchitectural features were varied. Barroso, Gharachorloo, and Bugnion [9] investigated database and Altavista search engine workloads on an SMP, focusing on the memory system performance. Other investigations using SimOS do not investigate OS activity at all [56, 85, 55, 34]. Web servers have been the subject of only limited study, due to their relatively recent emergence as a workload of interest. Hu, Nanda, and Yang [38] examined the Apache Web server on an IBM RS 6000 and an IBM SMP, using kernel instrumentation to profile kernel time. Although they execute on ....
OLUKOTUN, K., NAYFEH, B. A., HAMMOND, L., WILSON, K., AND CHANG, K. The case for a single-chip multiprocessor. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (October 1996).
An Energy Saving Strategy Based on Adaptive Loop.. - Kadayif, Kandemir, Karakoy (2002) (Correct)
....shut down and pre activation can be very effective in reducing energy consumption without increasing execution time. Our experiments with pre activation indicate a 39 reduction in energy consumption (on average) as compared to a scheme without energy management. Apart from academic interest ([11, 9]) chip multiprocessor architectures are also finding their ways into commercial products. For example, Sun s MAJC 5200 [10] is a general purpose multiprocessor system on a chip integrating two processors, a memory controller, a PCI controller, two high bandwidth I O controllers, a data transfer ....
....2. MPOC ARCHITECTURE We assume that a number of processors are integrated on a single die using an on chip cache memory architecture as shown in Figure 1. In this work, we assume that each processor has a simple pipelined architecture that issues one instruction per cycle. As stated in [11], using simple, identical processors allows the design and verification costs for a single CPU core to be lower, and amortizes those costs over a larger number of processor cores. We assume that each processor has its own data cache and instruction cache. While in this work we focus on a single ....
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single chip multiprocessor. In Proc. the 7th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1996, pp. 2--11.
Relational Profiling: Enabling Thread-Level Parallelism in.. - Heil, Smith (2000) (8 citations) (Correct)
....the Java compiler, and jack, a parser generator. Simulations began at about 10 million instructions before the first GC, until completion, except for javac, which was terminated at 200M cycles. 5. 4 Processor models Ways to exploit thread level parallelism include chip multiprocessing (CMP) [15] and multithreading. The particular design explored in this paper, Figure 6, uses finegrain multithreading (FGMT) 1] and CMP. On one chip, there is a large high ILP processor supplemented by three service processors. The computation of greatest concern, the application, runs on the high ILP ....
K. Olukotun et al., "The Case for a Single-Chip Multiprocessor," 7 Intl. Symp. on Architectural Support for Programming Languages and Operating Systems, pp. 211, Oct. 1996.
Exploiting Superword Level Parallelism with Multimedia.. - Larsen, Amarasinghe (2000) (20 citations) (Correct)
....will boost performance in next generation microprocessors. Current superscalar techniques are providing diminishing returns since they are unable to scale with the amount of available silicon. New architectures are emerging in an attempt to address this issue. Examples include chip multiprocessors [24] and RAW architectures [31] It will take time for these architectures and their associated compiler technology to mature. SLP execution, on the other hand, has already begun to appear in general purpose microprocessors. With the ability to automatically exploit this parallelism, such processors ....
Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a single-chip multiprocessor. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 2--11, Cambridge, Massachusetts, October 1--5, 1996.
Time-Shifted Modules: Exploiting Code Modularity for Fine.. - Zilles, Sohi (Correct)
.... prevalence of thread level parallelism (TLP) in server applications (e.g. databases, web servers) many next generation server processors will concurrently execute multiple threads in hardware [10, 11] using techniques like simultaneous multithreading (SMT) 30] and chip multi processing (CMP) [24]. Historically, technology developed for high end processors has been later deployed in commodity processors. Processor manufacturers often amortize design costs by reusing an existing processor core in a new market segment when process technology shrinks make it cost effective to do so. Thus, we ....
K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K.-Y. Chang. The Case for a Single-Chip Multiprocessor. In Proc. 7th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1996. 21
Workload Clustering for Increasing Energy - Savings On Embedded (Correct)
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K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single Chip Multiprocessor. Proceedings of ASPLOS'1996.
Hardware Support for Thread-Level Speculation - Steffan (2003) (Correct)
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K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of ASPLOS-VII, October 1996.
How Multithreading Addresses the Memory Wall - Philip Machanick School (Correct)
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Olukotun, K., Nayfeh, B. A., Hammond, L., Wilson, K., and Chang, K. (1996). The case for a single-chip multiprocessor. In Proc. 7th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-7), pages 2--11, Cambridge, MA.
Adaptive Explicitly Parallel Instruction Computing - Surendranath Talla Of (2000) (4 citations) (Correct)
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Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a single-chip multiprocessor. ACM SIGPLAN Notices, 31(9):2--11, September 1996.
Message-Passing Computer - Jignesh Shah Virginia (Correct)
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[15] K. Olukotun, B.A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The Case for a Single-Chip Multiprocessor," Seventh International Symp. Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), October 1996, pp. 2-11.
Area and System Clock Effects on SMT/CMP Processors - James Burns Jean-Luc (2000) (2 citations) (Correct)
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K. Olukotun, B. Nayfeh, L. Hammond, Ken Wilson, and Kunyung Chang, "The Case for a Single-Chip Multiprocessor." Proceedings Seventh International Symposium of Architectural Support for Programming Languages and Operating Systems (ASPLOS VII) 1996, http://www-hydra.standord.edu.
Latency Tolerant Architectures - Bennett (1998) (2 citations) (Correct)
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K. Olukotun, B. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single-chip multiprocessor. In SIGPLAN Notices, pages 2--11, Oct 1996.
Clustered Multithreaded Architectures - Pursuing Both IPC.. - Collins, Tullsen (2004) (Correct)
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K. Olukotun, B. Nayfeh, L. Hammond, K. Wilson, and K.-Y. Chang. The case for a single-chip multiprocessor. In Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1996.
What if DRAM is a Slow Peripheral? - Machanick (Correct)
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Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a singlechip multiprocessor. In Proc. 7th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-7), pages 2--11, Cambridge, MA, October 1996.
Dynamic Thread Resizing for Speculative Multithreaded Processors - Zahran, Franklin (Correct)
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K.Olukotun, B.A.Nayfeh, L.Hammond, K. Wilson, and K.Chang. The case for a single-chip multiprocessor. In Proc. 7th international conference on Architectual support for programming languages and operating systems(ASPLOS), 1996.
Hardware Support for Thread-Level Speculation - Steffan (2003) (Correct)
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K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of ASPLOS-VII, October 1996.
Exploiting Processor Workload Heterogeneity for.. - Kadayif.. (Correct)
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K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The Case for a Single Chip Multiprocessor. Proceedings of the 7th Intl Conference on Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1996, pp. 2--11.
Y-Branches: When You Come to a Fork in the Road, Take It - Nicholas Wang Michael (2003) (Correct)
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K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single-chip multiprocessor. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, 1996.
Exploiting Thread-Level Parallelism On . . . - Lo (1998) (Correct)
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K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang. The case for a single-chip multiprocessor. In Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 2--11, October 1996.
Using Software-Extended Architectures for Software.. - Witchel, Kaashoek (Correct)
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Basem A Nayfeh Kunle Olukotun, Lance Hammond, Ken Wilson, , and Kunyung Chang. The case for a single-chip multiprocessor. In Proceedings of ASPLOS-VII, Oct 1996.
ADAM: A Decentralized Parallel Computer Architecture Featuring.. - Huang (2002) (Correct)
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Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a single-chip multiprocessor. In Proceedings of ASPLOS-VII, Cambridge MA. ACM, 1996.
Exploring Thread-Level Speculation in Software: The.. - Papadimitriou, Mowry (2001) (Correct)
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Kunle Olukotun, Basem Nayfeh, Lance Hammond, Ken Wilson, and Kunyung Chang. The case for a single-chip multiprocessor. In Proceedings of the 7th Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.
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